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I 2 C

I2C is A Small Area Network connecting ICs and other electronic systems. The name stands for "inter - Integrated Circuit Bus" a variety of devices are available with I2C Interfaces.

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elumalaianitha
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228 views

I 2 C

I2C is A Small Area Network connecting ICs and other electronic systems. The name stands for "inter - Integrated Circuit Bus" a variety of devices are available with I2C Interfaces.

Uploaded by

elumalaianitha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 16

Development of Reusable Environment

for
I2C Protocol

PRESENTED BY:

SANKULA SIVA SANKAR


S.S.G.KRISHNA YADAV .K
KANCHI SRILATHA
V.VAMSI KRISHNA
M.NIKLESH REDDY

Project Guide:
PADMANABAN

Aim:
To verify I2C master

Objectives:
1.To conduct a literature survey to understand the functionality of I2C.
2.To define specifications.
3.To develop the simulation model of the I2C master DUT.
4.To develop the reusable verification Environment.
5.To analyze functional & code coverage reports.

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Introduction:

The name stands for Inter - Integrated Circuit Bus

A Small Area Network connecting ICs and other electronic systems

Originally intended for operation on one


single board / PCB
Synchronous Serial Signal
Two wires carry information between
a number of devices
One wire use for the data
One wire used for the clock

Today, a variety of devices are available with I2C Interfaces


Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Features:

Data transfer between ICs and systems at relatively low rates


Classic I2C is rated to 100K bits/second
Fast Mode devices support up to 400K bits/second
A High Speed Mode is defined for operation up to 3.4M bits/second

Reduces Board Space and Cost By:


Allowing use of ICs with fewer pins and smaller packages
Greatly reducing interconnect complexity
Allowing digitally controlled components to be located close to their point of
use.

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

I2C specification

Single master single slave

Synchronous

Bidirectional Serial Communication

7-bit addressing mode

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Master:

Initiates a transfer by generating


start and stop conditions
Generates the clock
Transmits the slave address
Determines data transfer direction

Slave:

Responds only when addressed


Timing is controlled by the clock line

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Top level diagram

MICRO
PROCESSOR

CLOC
K
RESE
T
ADDRES
S
DATA_IN
DATA_OUT

I2C
MASTER
CONTROLL
ER

SCL
SDA

R/W

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Pin Description
SIGNAL
NAME

SIGNAL
DIRECTION

DEFINITION

ACTIVE STATE

Clock

Input

Microprocessor
clock

N/A

Reset

Input

System reset

Active Low

Address

Input

Address bits
reading and
writing to
configuration
and data
registers

N/A

Data

Bi-directional

Data bus

N/A

RW

Input

SDA

Bi-directional

1/21/2015

SCL

1 = RD
0 = WR
I2C Data bus
line

Copyright CoreEL Technologies (I)


Pvt. Ltd.

Uni-directional

I2C Clock line

N/A

N/A

Operation of I2C Bus

Start Condition

Slave address + R/W


Slave acknowledges with ACK

All data bytes


Each followed by ACK

Stop Condition

SDA
ACK from
Slave

ACK from
Receiver

SCL
Start
1/21/2015

Remember : Clock is produced by


Master
Copyright CoreEL Technologies (I)
Pvt. Ltd.

Stop
9

WRITE OPERATION:

generate start command


write slave address + write bit
receive acknowledge from slave write data
receive acknowledge from slave
generate stop command

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

10

Read operation:
generate start bit
Read slave address + read bit
receive acknowledge from slave
Read data
Send acknowledge to slave
write no acknowledge (NACK) to slave,
indicating end of transfer
generate stop signal

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

11

TIMING DIAGRAM
CLK
RESE
T
R=1/W
=0
DATA_IN

D0

D1

D2

xxxx

xxxx

xxxx

ADD

A0

A1

A2

A3

A4

A5

xxxx

xxxx

xxxx

D7

D8

D9

DATA_OUT

Schedule:-Gantt chart

1/21/2015

Objectives

Phase-I

Survey

20-1-2015

specifications

27-1-2015

simulation

Will complete
by 6-2-2015

Phase-II

environment

14-2-2015

coverage

15-2-2015
Copyright CoreEL Technologies (I)
Pvt. Ltd.

13

Deliverables

verify model and DUT


Test plan and valid test cases
Environment using System Verilog
Code and Functional Coverage
reports

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

14

References

www.nxp.com
SPI vs I2C pdf
www.ti.com
www.opencores.org

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

15

1/21/2015

Copyright CoreEL Technologies (I)


Pvt. Ltd.

16

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