Design for Testability

Outline
Ad Hoc Design for Testability Techniques

Method of test points

Multiplexing and demultiplexing of test points
Time sharing of I/O for normal working and testing modes
Partitioning of registers and large combinational circuits

Scan-Path Design

Scan-path design concept

Controllability and observability by means of scan-path
Full and partial serial scan-paths
Non-serial scan design
Classical scan designs

Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Method of Test Points:
Block 1

Block 2

Block 1 is not observable,

Block 2 is not controllable

Improving controllability and observability:

OP
Block 1

CP
Block 1

Block 2

1- controllability:
CP = 0 - normal working mode
CP = 1 - controlling Block 2
with signal 1

Block 2

0- controllability:
CP = 1 - normal working mode
CP = 0 - controlling Block 2
with signal 0

OP
&

CP
Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Method of Test Points:
Block 1

Block 1 is not observable,

Block 2 is not controllable

Block 2

Improving controllability:

Block 1

CP1
Block 1

CP1
CP2

&

Block 2

CP2
MUX

Block 2

Normal working mode:

CP1 = 0, CP2 = 1
Controlling Block 2 with 1:
CP1 = 1, CP2 = 1
Controlling Block 2 with 0:
CP2 = 0
Normal working mode:
CP2 = 0
Controlling Block 2 with 1:
CP1 = 1, CP2 = 1
Controlling Block 2 with 0:
CP1 = 0, CP2 = 1

Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Multiplexing monitor points:
0
1

To reduce the number of

output pins for observing
monitor points,
multiplexer can be used:
2n observation points are
replaced by a single
output and n inputs to
address a selected
observation point

MUX
2n-1

x1
x2
xn

Disadvantage:
Only one observation
point can be observed at a
time

Number of additional pins:

(n + 1)
Number of observable points: [2n]
Advantage: (n + 1) << 2n
Technical University Tallinn, ESTONIA

OUT

Ad Hoc Design for Testability Techniques

Multiplexing monitor points:
To reduce the number of
output pins for observing
monitor points,
multiplexer can be used:

0
1

To reduce the number of

inputs, a counter (or a
shift register) can be used
to drive the address lines
of the multiplexer

2n-1

MUX

Counter

Disadvantage:
Only one observation
point can be observed at a
time

Number of additional pins:

2
Nmber of observable points: [2n]
Advantage: 2 << 2n
Technical University Tallinn, ESTONIA

OUT

Ad Hoc Design for Testability Techniques

Demultiplexer for implementing control points:
0

CP1
CP2

2n-1

CPN

DMUX

To reduce the number of

input pins for controlling
testpoints, demultiplexer
and a latch register can be
used.

Disadvantage:

x1
x2
xn
Number of additional pins:
Number of control points:

N clock times are required

between test vectors to
set up the proper control
values

(n + 1)
2n-1 N 2n

Advantage: (n + 1) << N

Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Demultiplexer for implementing control points:
0

CP1
CP2

2 -1

CPN

DMUX
n

To reduce the number of input

pins for controlling testpoints,
demultiplexer and a latch
register can be used.
To reduce the number of inputs
for addressing,
a counter
(or a shift register) can be used
to drive the address lines of
the demultiplexer

Counter

Disadvantage:
Number of additional pins:
Number of control points:

2
N

Advantage: 2 << N

N clock times are required

between test vectors to set up
the proper control values

Technical University Tallinn, ESTONIA

Time-sharing of outputs for monitoring

To reduce the number of
output pins for observing
monitor points, timesharing of working
outputs can be
introduced: no additional
outputs are needed

MUX

To reduce the number of

inputs, again counter or
shift register can be used
if needed

Number of additional pins:

Number of control points:

Original
circuit

1
N

Advantage: 1 << N
Technical University Tallinn, ESTONIA

Time-sharing of inputs for controlling

0

Normal
input
lines

CP1
CP2

CPN

To reduce the number of

input pins for controlling
test points, time-sharing
of working inputs can be
introduced.
To reduce the number of
inputs for driving the
address lines of
demultiplexer, counter or
shift register can be used
if needed

DMUX

Number of additional pins:

Number of control points:

1
N

Advantage: 1 << N

Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s

Given a circuit:
- CP1 and CP2 are not controllable
- CP3 and CP4 are not observable
DFT task: Improve the testability by using a single control input, no
additional inputs/outputs allowed
1
2
3
4

CP1
CP2
CP3
CP4

1
2
3
4

Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s

Given a circuit:
CP3 and CP4 are not observable
Improving the observability

Coding:

Mode

MUX

0
1

Norm.
Test

0
1

T
1
2
3
4

CP1
CP2
CP3
CP4

1
2
3
4

0
1 MUX
0
1 MUX

Result: A single pin T is needed

Technical University Tallinn, ESTONIA

Example: DFT with MUX-s and DMUX-s

Given a circuit: CP1 and CP2 are not controllable Improving the controllability
Coding:
T

Counter

0
DMUX
FF

1
0
DMUX 1
1

Result:
A single pin T
is needed

Mode DMUX MUX

00 Norm.
01 Contr
10 Test

Decoder

2
3
4

FF

0
1 MUX
0
1 MUX

CP1

CP2
CP3
CP4

1
0
1

2
3
4

Technical University Tallinn, ESTONIA

1
x
0

Example: DFT with MUX-s and DMUX-s

x1
x2
x3

F1
F2

z1
z2
z3

F3

z4

F4

y1

Counter
Counter
Decoder
Decoder

MUX

MUX

Mode

DMUX

00
000

Norm

001
0

Contr

010

Test

011
0

100

Obs
Obs

101
10

Obs

0
DMUX

DMUX
FF

FF

0
CP1
MUX 1

1 MUX1

1
0

Result:
A single
pin T
is needed

1
2
3

1
CP 2
CP 3

2
2
3
3
4

MUX 2

2 MUX 2
3

CP4

Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Examples of good candidates for control points:

control, address, and data bus lines on bus-structured designs

enable/hold inputs of microprocessors
enable and read/write inputs to memory devices
clock and preset/clear inputs to memory devices (flip-flops, counters, ...)
data select inputs to multiplexers and demultiplexers
control lines on tristate devices

Examples of good candidates for observation points:

stem lines associated with signals having high fanout

global feedback paths
redundant signal lines
outputs of logic devices having many inputs (multiplexers, parity generators)
outputs from state devices (flip-flops, counters, shift registers)
address, control and data busses

Technical University Tallinn, ESTONIA

Fault redundancy and testability

x1
x2

x4

&

&
&

y
x2

x4

&

Faults at x2 not
testable

x3
&

Fault at

&

&

y x1 ( x1 x2 ) x4 x3 x4
y
0
x2

x11

x1
x12

1
x3

&

Redundant gates are removed:

&
&

Remaining
gate
not testable
0

x12

y x1 x4 x3 x4 x1 x4 x3
Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Logical redundancy:
Redundancy should be avoided:

If a redundant fault occurs, it may invalidate

some test for nonredundant faults

Redundant faults cause difficulty in

calculating fault coverage

Much test generation time can be spent in

trying to generate a test for a redundant fault

Redundancy intentionally added:

To eliminate hazards in combinational

circuits
To achieve high reliability (using error
detecting circuits)

Hazard control circuitry:

1
0
0
1
&
1
1
1
T
& 0 1
1

&

Redundant AND-gate
Fault 0 not testable
Additional control input added:
T = 1 - normal working mode
T = 0 - testing mode
Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Fault redundancy:

Testable error control circuitry:

Error control circuitry:

Decoder
Decoder

1
No
error

E = 1 if decoder is fault-free
Fault 1 not testable

1
Error
detected

Additional control input added:

T 0 - normal working mode
T = 1 - testing mode
Technical University Tallinn, ESTONIA

Ad Hoc Design for Testability Techniques

Partitioning of registers (counters):
IN

CL

REG 1

OUT

IN
CL

16 bit counter divided

into two 8-bit counters:

REG 2

Instead of 216 = 65536

clocks, 2x28 = 512
clocks needed

OUT

If tested in parallel, only

256 clocks needed
CP: Data Inhibit

CP: Tester Data

&

&

CP: Data Inhibit

IN
CL

C
&
CP: Clock Inhibit

REG 1

OUT

CP: Tester Data

&

&

IN
CL

REG 2

&
OP

CP: Tester Clock

Technical University Tallinn, ESTONIA

OUT

Ad Hoc Design for Testability Techniques

Partitioning of large combinational circuits:

C1

DMUX1

MUX3

The time complexity of

test generation and
fault simulation grows
faster than a linear
function of circuit size
Partioning of large
circuits reduces these
costs

C1
MUX1

MUX2

I/O sharing of normal

and testing modes is
used

C2
DMUX2

C2

MUX4

Three modes can be

chosen:
- normal mode
- testing C1
- testing C2 (bolded
lines)

How many additional inputs are needed?

Technical University Tallinn, ESTONIA

Scan-Path Design
IN

OUT

Combinational
circuit

The longer a feedback loop, the more

clock cycles are needed to initialize
and sensitize patterns

Scan-IN
q

The complexity of testing is a function

of the number of feedback loops and
their length

Scan-register is a aregister with

both shift and parallel-load capability
T = 0 - normal working mode

Scan-OUT

T = 1 - scan mode

Normal mode :

&

Scan-IN

&

flip-flops are
connected to the combinational circuit

D T

C
Scan-OUT

Test mode:

flip-flops are
disconnected from the combinational
circuit and connected to each other to
form a shift register

Technical University Tallinn, ESTONIA

Scan-Path Design and Testability

Two possibilities for improving
controllability/observability

MUX

IN

SCAN
OUT

OUT

DMUX
SCAN
IN

Technical University Tallinn, ESTONIA

Parallel Scan-Path
IN

Combinational
circuit

Scan-IN 1

R1

Scan-OUT 1

In parallel scan
path flip-flops can
be organized in more
than one scan chain
Advantage: time

Scan-IN 2

R2
Scan-OUT 2

OUT

Disadvantage: #
pins

Technical University Tallinn, ESTONIA

Partial Scan-Path
IN

Combinational
circuit

Scan-IN

R1

Scan-OUT

R2

OUT

In partial
scan instead
of
fullscan,
it
may be
advantageous
to scan
only some
of the flipflops

Example:
counter
even bits
joined in the
Technical University Tallinn, ESTONIA

Partial Scan Path

Scan-In

Hierarhical test generation with Scan-Path:

R2

Control Part

y4

0
1
2

y1

R1

y3

M1

c
M3

y3

R2

Bus

y1

R1 + R2
1

b
M2

y4

R2

Scan-Out

IN

y2

2
3

IN
R1
y2

0
1

Data Part

IN + R2

R1 * R2
IN* R2

Technical University Tallinn, ESTONIA

Testing with Minimal DFT

Hierarhical test generation with Scan-Path:
R2

Control Part

y4

0
1

Scan-In
y1

R1

y3

M1

c
M3

y3

R2

Bus

y1

R1 + R2
1

b
M2

y4

R2

Scan-Out

IN

y2

2
3

IN
R1
y2

0
1

Data Part

IN + R2

R1 * R2
IN* R2

Technical University Tallinn, ESTONIA

Random Access Scan

IN

q
Scan-IN
Scan-CL

OUT

Combinational
circuit

&
Scan-OUT

X-Address

DC

In random
access scan
each flip-flop in
a logic network
is selected
individually by
an address for
control and
observation of
its state
Example:

Y-Address

DC

Delay fault
testing
Technical University Tallinn, ESTONIA

Improving Testability by Inserting CPs

Two possibilities for improving
controllability/observability

MUX

IN

SCAN
OUT

OUT

DMUX
SCAN
IN

Technical University Tallinn, ESTONIA

Selection of Test Points

Test point selection approaches
Improving testability for any set of pseudo-random patterns
(Pseudorandom BIST)
Testability measures are used to characterize the controllability and
observability of the circuit

Improving testability for a given sequence of vectors

(Functional BIST)
Fault simulation is used for measuring the fault coverage

Methods that are used:

logic simulation,
fault simulation,
estimation of controllability and observability values,
path tracing
Technical University Tallinn, ESTONIA

Random BIST vs Functional BIST

Random
BIST

Traditional
functional
testing

Test
generator

HW
overhead

UUT

Normal
operation

Signature

Go/NoGo

Reference

Random test set

Functional
BIST

UUT

UUT

Result

Result

Reference

Go/NoGo

HW
overhead

Signature

Go/NoGo

Reference

Deterministic
functional test set
Technical University Tallinn, ESTONIA

Improving Testability by Inserting CPs

Circuit

Test
sequence

Fault
coverage
100%

Fault
Simulation

Not
detected
faults

Circuit
modification

Selection
of CPs
Technical University Tallinn, ESTONIA

Functional BIST

Technical University Tallinn, ESTONIA

Selection of Test Points

Method: Simulation of given test patterns
Identification of the faults that are detected
The remaining faults are classified as
A: Faults that were not excited
B: Faults at gate inputs that were excited but not propagated to the gate output
C: Faults that were excited but not propagated to circuit output

The faults A and B require control points for their detection

The faults C may be detected by either by observation points or by
control points
Control points selection should be carried out before observation
points selection

Technical University Tallinn, ESTONIA

Classification of Not-Detected Faults

Class C:
Classes
A and B
need
controllability

Faults at x1 are not

propagated to the output

x1
x2
x3

Always 1

Class A:
Fault x3 1 is not
activated

x4
x5

1
0

&
Class B:

Class C needs
either
controllability
or
observability

Faults at x5 are not

propagated
through the gate
Technical University Tallinn, ESTONIA

Selection of Test Points

Classification of faults

x1
x2
x3

Given test:
Test patterns
No

Inputs

Intern.
points

Inputs

1 2 3 4 5 a b c 1 2 3 4 5 a b c

0 0 1 0 1 0 0 0 1 1 - 1 -

0 1 0 1 1 1 0 1 - - - 0 0 -

- 0

0 1 0 1 0 1 0 0 - - 1 -

1 1

x1/0 x2/0 x3/0 a /0 b /0

1 1 1

1 -

&
x4
x5

Fault table
Intern.
points

1
&

Not detected faults:

Class Faults

Missing signals

x1/0:

x1 = 1

is missing

b /0:

b =1

is missing

x3/0:

x3 a = 11 is missing

a /0:

x3 a = 11 is missing

x2/0:

x1x2= 01

Technical University Tallinn, ESTONIA

OK

Selection of Test Points

Classification of faults

x1
x2
x3

Given test:
Test patterns
No

Inputs

Intern.
points

Inputs

1 2 3 4 5 a b c 1 2 3 4 5

a b c

0 0 1 0 1 0 0 0 1 1 - 1 -

1 1 1

0 1 0 1 1 1 0 1 - - - 0 0

- - 0

0 1 0 1 0 1 0 0 - - 1 -

- 1 1

x1/0 x2/0 x3/0 a /0 b /0

&
x4
x5

Fault table
Intern.
points

b
1

&

Not detected faults:

Class Faults

Missing signals

x1/0:

x1 = 1

is missing

b /0:

b =1

is missing

x3/0:

x3 a = 11 is missing

a /0:

x3 a = 11 is missing

x2/0:

x1x2= 01

Technical University Tallinn, ESTONIA

OK

Selection of Test Points

Classification of faults

x1
x2
x3

Given test:
Test patterns
No

Inputs

Intern.
points

Inputs

1 2 3 4 5 a b c 1 2 3 4 5 a b c

&
x4
x5

Fault table
Intern.
points

1
&

Not detected faults:

Class Faults

Missing signals

x1/0:

x1 = 1

is missing

b /0:

b =1

is missing

0 0 1 0 1 0 0 0 1 1 - 1 -

0 1 0 1 1 1 0 1 - - - 0 0 -

- 0

0 1 0 1 0 1 0 0 - - 1 -

1 1

x3/0:

x3 a = 11 is missing

a /0:

x3 a = 11 is missing

x2/0:

x1x2= 01

x1/0 x2/0 x3/0 a /0 b /0

1 1 1

1 -

Technical University Tallinn, ESTONIA

OK

Selection of Test Points

Classification of faults

x1
x2
x3

Given test:
Test patterns
No

Inputs

Intern.
points

Inputs

1 2 3 4 5 a b c 1 2 3 4 5 a b c

&
x4
x5

Fault table
Intern.
points

1
&

Not detected faults:

Class Faults

Missing signals

x1/0:

x1 = 1

is missing

b /0:

b =1

is missing

0 0 1 0 1 0 0 0 1 1 - 1 -

0 1 0 1 1 1 0 1 - - - 0 0 -

- 0

0 1 0 1 0 1 0 0 - - 1 -

1 1

x3/0:

x3 a = 11 is missing

a /0:

x3 a = 11 is missing

x2/0:

x1x2= 01

x1/0 x2/0 x3/0 a /0 b /0

1 1 1

1 -

Technical University Tallinn, ESTONIA

OK

Selection of Test Points

Classification of faults

x1
x2
x3

Given test:
Test patterns
No

Inputs

Intern.
points

Inputs

1 2 3 4 5 a b c 1 2 3 4 5 a b c

0 0 1 0 1 0 0 0 1 1 - 1 -

0 1 0 1 1 1 0 1 - - - 0 0 -

0 1 0 1 0 1 0 0 - - 1 -

x1/0 x2/0 x3/0 a /0 b /0

&

1
&

Not detected faults:

Class Faults
A
x1/0:

Missing signals
x1 = 1
is missing

b /0:

b =1

- 0

x3/0:

x3 a = 11 is missing

1 1

a /0:

x3 a = 11 is missing

x2/0:

x1x2= 01

1 1 1

1 -

1
x4
x5

Fault table
Intern.
points

is missing

OK, but

path activation is missing

Technical University Tallinn, ESTONIA

Selection of Test Points: Procedure

1. Selection of control points:
Once control point candidates are identified for the faults A and B, a
minimum number of control points (CP) can be identified
This can be formulated as a minimum coverage problem where a
minimum CPs are selected such that at least one CP candidate is
included for each fault in A and B
F1

Control
point
candidates

CP1

CP2

CP3

F3

F4

F6

F7

F8

1
1

1
1

F5

CP4
CP5

F2

F9

1
1

1
1

1
1

Faults

Selected
control
points

Technical University Tallinn, ESTONIA

Selection of Test Points: Procedure

2. Selection of observation points
Once the CPs are selected, the given test patterns are augmented to
accommodate the additional inputs assotiated with the CPs and
fault simulation is performed
The fault class C is updated
For each fault, in C the circuit lines to which the effect of the fault
propagates, are identified as a potential observation point candidates
A minimum covering problem is formulated and solved to find the
observation points to be added

Minimization of control points

New fault simulation

Control
Test

DMUX

CP1
CP2
CPN

F1

Fault
class C
updated

CP1

CP2

CP3

F3

F4

F6

F7

F8

1
1

1
1

F5

CP4
CP5

F2

F9

1
1

1
1

Technical University Tallinn, ESTONIA

1
1

Selection of Test Points

x1/0

Minimization of test points:

x1
x2

Not detected faults:

Class A: x1/0, b /0
Class B: x3/0, a /0,

x3

1
x3/0

Test point coverage:

To be selected

Potential
control
points

Not detected faults

x3/0

a /0

b /0

x3=1

a =1

b =1

a /0

x4
x5

&

b
b /0

&

Test patterns

x1/0

x1=1

No

Inputs

Intern.
points

1 2 3 4 5 a b c

0 0 1 0 1 0 0 0

0 1 0 1 1 1 0 1

0 1 0 1 0 1 0 0

Technical University Tallinn, ESTONIA

Insertion of Test Points

x1/0

x1
x2

Two test points:

Selected test points:
Class A: x1/0 x1=1 (control point)
Class C: x2/0 (observable point)

x2/0

x3

No

Inputs

Intern.
points

This
pattern is
to be
repeated
with

0 0 1 0 1 0 0 0

T1=1

0 1 0 1 1 1 0 1

0 1 0 1 0 1 0 0

1 2 3 4 5 a b c

x3/0

a /0

&

b /0

x4
x5

&

Corrected circuit:

Test patterns

T1=1

x1
T1=1

1
x2
x3

T2

x1/0

T2

&

x2/0

x4
x5

1
&

To be observed
Technical University Tallinn, ESTONIA

Selection of Test Points

Minimization of monitoring points:

Space

Additional
outputs

MUX

To reduce the number of output

pins for observing monitor points,
exor gates can be used:

0
1

MUX
2n-1

Space and time

compaction

EXOR

With MUX
With EXOR

OUT

Time

Without MUX

Counter

Technical University Tallinn, ESTONIA

OUT

Selection of Test Points

Minimization of monitor points:
To reduce the number of output
pins for observing monitor points,
signature analyzers can be used:

Space

Additional
outputs

Additional time
compaction

MUX
EXOR

With SA
With EXOR

Time
With MUX
SCAN OUT

0
1

MUX
2n-1

OUT

SA

Counter
SCAN IN
Technical University Tallinn, ESTONIA

Boundary Scan Standard

Technical University Tallinn, ESTONIA

Boundary Scan Architecture

internal
logic

T
TDO
A
P

Data_in
TDI

BSC

TDO

TDI
TMS

internal
logic

TCK
TDO

T
A
P

internal
logic

T
A
P

TDI
T
A
P

internal
logic

T
A
P

TMS
TCK
TDO

internal
logic

Data_out

Technical University Tallinn, ESTONIA

TDI

Scan
Internal
logic

Registers

Boundary

Boundary Scan Architecture

Data
Register
s

Device ID. Register

Bypass Register
TDO
Instruction Register (IR)

Technical University Tallinn, ESTONIA

Boundary Scan Cell

To next cell

From system
pin

To
system
logic

0
1

0
1
From
last
cell

SET

CLR

Shift
DR

Q
Q

Clock DR
For SHIFT

SET

CLR

Q
Q

Test/Normal

Update
DR
For HOLD

Used at the input or output pins

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

SAMPLE mode:
Get snapshot of normal chip output signals

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

PRELOAD mode:
Put data on boundary scan chain before next instruction

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

Extest instruction:
Test off-chip circuits and board-level interconnections

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

INTEST instruction
Feeds external test patterns in and shifts responses out

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

Bypass instruction:
Bypasses the
corresponding chip
using 1-bit register

From TDI
Shift DR

SET

To TDO

Clock DR

CLR

Technical University Tallinn, ESTONIA

Boundary Scan Working Modes

IDCODE instruction:
Connects the component device identification register serially
between TDI and TDO in the Shift-DR TAP controller state
Allows board-level test controller or external tester to read out
component ID
Required whenever a JEDEC identification register is included
in the design
TDI

Version

Part Number

Manufacturer ID

4-bits
Any format

16-bits
Any format

11-bits
Coded form of JEDEC

TDO

Technical University Tallinn, ESTONIA

Fault Diagnosis with Boundary Scan

Short
1

0
Assume wired
AND

0
Open
Assume stuck-at-0

Technical University Tallinn, ESTONIA

Fault Diagnosis with Boundary Scan

Short
10

00

01

00

00

Assume wired
AND

11

00
00

Open
Assume stuck-at-0

Kautz showed in 1974 that a sufficient condition to detect any pair of

short circuited nets was that the horizontal codes must be unique for
all nets. Therefore the test length is ]log2(N)[
Technical University Tallinn, ESTONIA

Fault Diagnosis with Boundary Scan

Short
101

001

011

001

001

Assume wired
AND

110
Open

Suspected
Wired AND
short

001

Ambiguiety

000

Suspected
open fault
SAF/0

Assume stuck-at-0

All 0-s and all 1-s are forbidden codes because of stuck-at faults
Therefore the final test length is ]log2(N+2)[
Technical University Tallinn, ESTONIA

Fault Diagnosis with Boundary Scan

Short
0 101

0 001

0 011

0 001

1 001

Assume wired
AND

1 110
Open

Suspected
Wired AND
short

1 001

Ambiguiety
solved

0 000

Suspected
open fault
SAF/0

Assume stuck-at-0

To improve the diagnostic resolution we have to add one bit more

Technical University Tallinn, ESTONIA

Synthesis of Testable Circuits

y x1 x3 x1 x2
x1

&

x3

&

x2

Test generation:

y x1 x3 x1 x2 x1 x2 x3 y

&
1
&

0
1
1
0

1
0
1
0

1
0
0
1

0
1
0
1

1
0
0
1

0
1
0
1

0
1
1
1

4 test patterns are needed

Technical University Tallinn, ESTONIA

0
0
1
1

Synthesis of Testable Circuits

Two implementations for the same circuit:
x1 x2 x3

011
110

y x1 x3 x1 x2
x1
x3
x2

&

011
110 &

&
1

&

Here:

4 test patterns are needed

101
110 &

&

First assignment

Here:

Only 3 test patterns are needed

Technical University Tallinn, ESTONIA

Synthesis of Testable Circuits

Given:

y x1 x3 x1 x2

y c0 c1 x3 c2 x2 c3 x2 x3 c4 x1 c5 x1 x3 c6 x1 x2 c7 x1 x2 x3
Calculation of constants:

fi x1 x2 x3 y
f0
f1
0
f3
f4
f5
f6
f7

0 0
0 0
1 0
0 1
1 0
1 0
1 1
1 1

0
1
1
1
0
1
0
1

1
0
0
0
0
0
1
1

1 C 0 = f0
1 C 1 = f0
C 2 = f 0 f2
0 C 3 = f0
1 C 4 = f0
1 C 5 = f0
1 C 6 = f0
0 C 3 = f0

New:

y 1 x3 x1 x1 x3 x1 x2
f1
f1
f4
f1
f2
f1

f2
f2 f3
f4 f5
f4 f6
f2 f3 f4 f5 f6 f7
Technical University Tallinn, ESTONIA

Synthesis of Testable Circuits

Test generation method:

Roles of test patterns:

y 1 x3 x1 x1 x3 x1 x2
&

x1 x2 x3

x1 x2 x3

011
110
011
110 &
101
110 &

(0
1

0
1

0)
1

0
1
1

1
0
1

1
1
0

0 &

1 &

Technical University Tallinn, ESTONIA

Testability as a trade-off
Amusing testability:
Theorem:
Proof:

You can test an arbitrary digital system by only 3 test patterns

if you design it approprietly
011

&

101

011
101

011

001

&

001
010

&

101

001
?

&

011
101

&

001

Solution: System FSM Scan-Path CC NAND

Technical University Tallinn, ESTONIA