Testing Semiconductor

Memories
Cheng-Wen Wu
Lab for Reliable Computing
Dept. Electrical Engineering
National Tsing Hua University

Outline
Introduction
RAM functional fault models and test
algorithms
RAM fault-coverage analysis
Cocktail-March for testing word-oriented
memories
Testing multi-port RAMs
Testing CAMs
Testing flash memories
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Cheng-Wen Wu, NT

Introduction
Memory testing is a more and more important issue

RAMs are key components for electronic systems

Memories represent about 30% of the semiconductor market
Embedded memories are dominating the chip yield

Memory testing is more and more difficult

Growing density, capacity, and speed

Emerging new architectures and technologies
Embedded memories: access, diagnostics & repair, heterogeneity,

custom design, power & noise, scheduling, compression, etc.

Cost drives the need for more efficient test methodologies

IFA, fault modeling and simulation, test algorithm development and

evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc.

Test automation is required

Failure analysis, fault simulation, ATG, and diagnostics
BIST/BIRA/BISR generation

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Typical RAM Production Flow

Wafer

Full Probe Test

Marking

Final Test

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Laser Repair

Post-BI Test

Burn-In (BI)

Visual Inspection

QA Sample Test

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Packaging

Pre-BI Test

Shipping

Scope of RAM Testing

Parametric Test: DC & AC
Reliability Screening

Long-cycle testing
Burn-in: static & dynamic BI

Functional Test

Device characterization
Failure analysis
Fault modeling
Simple but effective (accurate & realistic?)
Test algorithm generation
Small number of test patterns (data backgrounds)
High fault coverage
Short test time

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RAM Models
Behavior Level

Verilog/VHDL

Function Level

Verilog/VHDL/Block diagram
Normally not synthesizable

Circuit Level

Spice/Schematic

Layout Level

GDS-II/Geometry

Who should provide the model?

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Memory Function Model Example

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RAM Fault Models (Static)

Address-Decoder Fault (AF)

No cell accessed by certain address

Multiple cells accessed by certain address
Certain cell not accessed by any address

Certain cell accessed by multiple addresses

Stuck-At Fault (SAF)

Cell (line) SA0 or SA1

Transition Fault (TF)

Cell fails to transit from 0 to 1 or 1 to 0

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RAM Fault Models (Static)

Bridging Fault (BF)

Short between cells

AND type or OR type

Stuck-Open Fault (SOF)

Cell not accessible due to broken line

Neighborhood Pattern Sensitive Fault (NPSF)

Active (Dynamic) NPSF
Passive NPSF
Static NPSF

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N
W BC E
S

RAM Fault Models (Static)

Coupling Fault (CF)
State Coupling Fault (CFst)
Coupled (victim) cell is forced to 0 or 1 if coupling
(aggressor) cell is in given state
Inversion Coupling Fault (CFin)
Transition in coupling cell complements (inverts)
coupled cell
Idempotent Coupling Fault (CFid)
Coupled cell is forced to 0 or 1 if coupling cell
transits from 0 to 1 or 1 to 0

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RAM Fault Models (Dynamic)

Recovery Fault (RF)

Sense Amplifier Recovery Fault (SARF)

Sense amp saturation after reading/writing long run
of 0 or 1
Write Recovery Fault (WRF)
Write followed by reading/writing at different location
resulting in reading/writing at same location
Write-after-write recovery fault
Read-after-write recovery fault

Results in functional faults---detected at high speed

(e.g., GALROW/GALCOL)

Disturb Fault (DF)

Victim cell forced to 0 or 1 if we read or write

aggressor cell (may be the same cell)

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RAM Fault Models (Dynamic)

Data Retention Fault (DRF)
DRAM
Refresh Fault

Refresh-Line Stuck-At Fault

Leakage Fault

Sleeping Sickness---loose data in less than

specified hold time (typically tens of ms)

SRAM
Leakage Fault

Static Data Losses---defective pull-up

Checkerboard pattern triggers max leakage

BIST good for sync with refresh mechanism

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Test Time Complexity (100MHz)

Size

10N

NlogN

1M

0.01s

0.1s

16M

0.16s

64M

1.5

0.2s

11s

3h

1.6s

3.9s

11m

33d

0.66s

6.6s

17s

1.5h

1.43y

256M

2.62s

26s

1.23m

12h

23y

1G

10.5s

1.8m

5.3m

4d

366y

4G

42s

7m

22.4m

32d

57c

16G

2.8m

28m

1.6h

255d

915c

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RAM Test Algorithm

A test algorithm (or simply test) is a finite
sequence of test elements

A test element contains a number of memory

operations (access commands)

Data pattern (background) specified for the Read

operation
Address (sequence) specified for the Read and
Write operations

A march test algorithm is a finite sequence of

march elements

A march element is specified by an address order

and a number of Read/Write operations

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Classical Test Algorithms

Zero-One Algorithm [Breuer & Friedman 1976]
Also known as MSCAN
For SAF
Solid background (pattern)
Complexity is 4N

{ ( w0); ( r 0); ( w1); ( r1)}

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Classical Test Algorithms

Checkerboard Algorithm
Zero-one algorithm with checkerboard pattern
Complexity is 4N
For SAF and DRF

1 0 1
0 1 0
1 0 1

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Classical Test Algorithms

Galloping Pattern (GALPAT)

Complexity is 4N**2---only for characterization

All AFs,TFs, CFs, and SAFs are located

1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC;
For OC = 0 to N-1, OC != BC;

BC

{ Read BC; Read OC; }

Complement BC; }
3. Write background 1;
4. Repeat Step 2;
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Classical Test Algorithms

Sliding (Galloping) Row/Column/Diagonal

Based on GALPAT, but instead of a bit, a complete

row, column, or diagonal is shifted

Complexity is 4N**1.5

1
1
1
1
1

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Classical Test Algorithms

Butterfly Algorithm

Complexity is 5NlogN

1. Write background 0;
2. For BC = 0 to N-1
{ Complement BC; dist = 1;
While dist <= mdist /* mdist < 0.5 col/row length
*/
6
{ Read cell @ dist north from BC;
1
Read cell @ dist east from BC;
9
4
5,10
Read cell @ dist south from BC;
3
Read cell @ dist west from BC;
Read BC; dist *= 2; }
8
Complement BC; }
3. Write background 1; repeat Step 2;

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Classical Test Algorithms

Moving Inversion (MOVI) Algorithm [De Jonge &
Smeulders 1976]

For functional and AC parametric test

Functional (13N): for AF, SAF, TF, and most CF

{ ( w0); ( r 0, w1, r1); ( r1, w0, r 0); ( r 0, w1, r1); ( r1, w0, r 0)}
Parametric (12NlogN): for Read access time

2 successive Reads @ 2 different addresses with

different data for all 2-address sequences differing
in 1 bit
Repeat T2~T5 for each address bit
GALPAT---all 2-address sequences

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Classical Test Algorithms

Surround Disturb Algorithm

Examine how the cells in a row are affected when

complementary data are written into adjacent cells

of neighboring rows

1. For each cell[p,q] /* row p and column q */

{ Write 0 in cell[p,q-1];
Write 0 in cell[p,q];
Write 0 in cell[p,q+1];
Write 1 in cell[p-1,q];
Read 0 from cell[p,q+1];
Write 1 in cell[p+1,q];
Read 0 from cell[p,q-1];
Read 0 from cell[p,q]; }
2. Repeat Step 1 with complementary data;

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1
0

21

Classical Test Algorithms

Zero-one and checkerboard algorithms do not
have sufficient coverage
Other algorithms are too time-consuming for large
RAM
Test time is the key factor of test cost
Complexity ranges from N2 to NlogN

Need linear-time test algorithms with small

constants
March test algorithms

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March Tests
Zero-One (MSCAN) { ( w0); ( r 0); ( w1); ( r1)}
Modified Algorithmic Test Sequence (MATS)
Thatte & Abraham 1979]

[Nair,

OR-type address decoder fault

{ ( w0); ( r 0, w1); ( r1)}

AND-type address decoder fault

{ ( w1); ( r1, w0); ( r 0)}

MATS+ [Abadir & Reghbati 1983]

For both OR- & AND-type AFs and SAF

{ ( w0); ( r 0, w1); ( r1, w0)}

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March Tests
Marching 1/0 [Breuer & Friedman 1976]
For AF, SAF, and TF

{ ( w0); ( r 0, w1, r1); ( r1, w0, r 0);

( w1); ( r1, w0, r 0); ( r 0, w1, r1)}

MATS++ [Goor 1991]

Also for AF, SAF, and TF

Complete and irredundant

{ ( w0); ( r 0, w1); ( r1, w0, r 0)}

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March Tests
March X

For AF, SAF, TF, & CFin

{ ( w0); ( r 0, w1); ( r1, w0); ( r 0)}

March C [Marinescu 1982]

For AF, SAF, TF, & all CFs---redundant

{ ( w0); ( r 0, w1); ( r1, w0);

( r 0); ( r 0, w1); ( r1, w0); ( r 0)}

March C- [Goor 1991]

Also for AF, SAF, TF, & all CFs---irredundant

{ ( w0); ( r 0, w1); ( r1, w0);

( r 0, w1); ( r1, w0); ( r 0)}
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March Tests
Limitations

Sequential faults in address decoders

RF
NPSF
(9N-2) for 2-CF [Marinescu 1982]
(2NlogN+11N) for 3-CF [Cockburn 1994]

Solutions

Address sequence variation

Hopping
Pseudorandom

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Coverage of March Tests

SAF
TF
AF
SOF
CFin
CFid
CFst

MATS++ March X March Y March C1

1
1
1
1
1
1
1
1
1
1
1
1
.002
1
.002
.75
1
1
1
.375
.5
.5
1
.5
.625
.625
1

Extended March C- (11N) has a 100% coverage of SOF

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Testing Word-Oriented RAM

Background bit is replaced by background word
MATS++:

{ ( wa ); ( ra, wa ' ); ( ra ' , wa, ra )}

Conventional method is to use logm+1 different

backgrounds for m-bit words
m=8: 00000000, 01010101, 00110011, and

00001111

Apply the test algorithm logm+1=4 times, so

complexity is 4*6N/8=3N

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Cocktail-March Algorithms
Motivation:
Repeating the same algorithm for all logm+1

backgrounds has redundancy

Different algorithm targets different faults

Approach:
Use multiple backgrounds in a single algorithm run
Merge and forge different algorithms and

backgrounds into a single algorithm

Good for word-oriented memories

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March-CW
Algorithm:

March C- for solid background (0000)

Then a 5N March for each of other standard

backgrounds (0101, 0011):

Result:

{ ( wa, wa ' , ra ' , wa, ra )}

Complexity is (10+5logW)N, where W is word

length and N is word count

Test time is reduced by 39% if W=4, as compared
with extended March C Improvement increases as W increases

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Comparison (Full Coverage)

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Testing NPSF
NPSF test approaches

Tiling
Multi-background march
Easy BIST implementation

5-cell neighborhood
B
E
S
N
W
B
S

Base cell: B
Deleted neighborhood cells: N, E, W, S
Neighborhood cells: and
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N
B

N, E, W, S

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NPSF Models
Static NPSF (SNPSF)
BC forced to a certain state due to a certain deleted

neighborhood (DN) pattern

Passive NPSF (PNPSF)

BC frozen due to a certain DN pattern

Active NPSF (ANPSF)

BC content changes due to a change in DN pattern
Change: a transition in one DN cell, with other DN cells & BC
containing a certain pattern

Assumptions:
Single NPSF
Address scramble table is available
Memory is bit-oriented
Word-oriented memory is tested as multiple bit-oriented ones

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Test Strategy
Multi-Background March
To generate all neighborhood patterns
Solid BG
(FC < 30%)

Another BG

0 0 0
0 0 0
0 0 0

0 0 0
0 X 0
0 0 0

0 0 0
0 X 1
1 1 1

1 1 1
1 X 0
0 0 0

1 1 1
1 X 1
1 1 1

1 0 1
1 0 1
1 0 1

1 0 1
1 X 1
1 0 1

0 1 0
0 X 0
0 1 0

0 1 0
0 X 1
1 0 1

1 0 1
1 X 0
0 1 0

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Testing PNPSF
March 17N:
( wa);
( wb, ra, wa);
( rb, wa);
(ra, wb);

( ra, ); wb
(rb, wa);

(rb, wa, ra, wb);

(ra)

Alg1:

March Elements
(w0);
(w1, r1, w0);

(r0);

NWBES
00
00

Alg2:

(w1);

(w0, r0, w1);

(r1);

11

11

Alg3:
Alg4:

(w0);
(w1);

(w1);
(w0);

(r1);
(r0);

11
11

00
00

Alg5:

(w0);

(w1);

(r1);

00

11

Alg6:

(w1);

(w0);

(r0);

00

11

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Data Background Generation

Data backgrounds
BG1: all zero
BG2: Ar[0], LSB of row address
BG3: Ar[1], second bit of row address
BG4: Ar[0]Ar[1]

00
01
10
11

00 01 10 11
0 0
0 0
0 0
0 0
BG.1

0
0
0
0

0
0
0
0

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00
01
10
11

00 01 10 11
0 0
1 1
0 0
1 1
BG.2

0
1
0
1

0
1
0
1

00
01
10
11

00 01 10 11
0 0
0 0
1 1
1 1
BG.3

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0
0
1
1

0
0
1
1

00
01
10
11

00 01 10 11
0 0
1 1
1 1
0 0
BG.4

0
1
1
0

0
1
1
0

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Testing ANPSF
(w0) ;

(w1) ;

(w0) ;

( r0,w1,w0) ;

(r0)

( r1,w0,w1) ;

( r0,w1) ;

(r1)

( r1,w0) ;

(r0)

0 0 0
0

0
0 0
0

0
0 0 0

0
0 0
0

1 1 1
1

1
1 1
1

1
1 1 1

1
1 1
1

0
1 1
1

0
0 0
1

1
0 0
0

1
1 1
0

March 12N:

(wa);
(rb, wa);
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(wb, ra, wa);

(ra, wb);

(rb, wa, wb);

(ra)
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Time Complexity
00
01
10
11

00
01
10
11

00 01 10 11
0 0
0 0
0 0
0 0

0
0
0
0

0
0
0
0

00
01
10
11

00 01 10 11
0 1
1 0
0 1
1 0

0
1
0
1

1
0
1
0

00
01
10
11

00 01 10 11
0 0
1 1
0 0
1 1

0
1
0
1

0
1
0
1

00
01
10
11

00 01 10 11
0 1
0 1
0 1
0 1

BG.1

BG.2

BG.3

BG.4

00 01 10 11
0 0
0 0
0 0
0 0

00 01 10 11
0 0
1 1
0 0
1 1

00 01 10 11
0 1
0 1
0 1
0 1

00 01 10 11
0 1
1 0
0 1
1 0

1
1
1
1

1
1
1
1

BG.5

00
01
10
11

1
0
1
0

1
0
1
0

BG.6

00
01
10
11

BG.7

1
1
1
1

0
0
0
0

00
01
10
11

0
0
0
0

1
1
1
1

1
0
1
0

0
1
0
1

BG.8

12 N/BG X 8 BG = 96N
Detects all NPSFs
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Multi-Port Memories
Popular architectures
k-port (k > 1)
n-read-1-write
FIFO

Port A

Address A
Data A
Control A

Storage
Address B

Port B

Data B
Control B

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2-Port Topology
BL
WL

BL

Interport WL short
WL A

WL
WL

BL

BL

WL

WL

WL

WL

Interport BL short
A

BL
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BL

BL

BL

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Inter-Port Word-Line Short

Fault-Free

Port A

Port B

Address 1

Address 2

Faulty

Cell 1

Address 1

Cell 1

Address 2

Cell 2

Address 3

Cell 3

Cell 2

* Functional test complexity: O(N3)

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Inter-Port Bit-Line Short

Fault-Free
Port A

Port B

Address

Address

Faulty
Cell

Cell

Address

Cell

Address

Cell

Address

Cell

Address

Cell

* Functional test complexity: O(N2)

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Address Scrambling
Logical Addr

A - word line select

B - I/O select
C - bit line select

Physical Addr

row

D - bit position in a word

column

Address A
bit3

bit2

bit1

bit0

Data word A
3

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Reading Neighboring Cells

Read neighboring cells to detect inter-port faults:
rN, rS, rE, and rW

N
W

B
S

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0/1
0/1

1/0

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TAGS-PS
March Test
Section 1
Port 1

Section 2
Multi-port
AF Test

Single-port
Test Algorithm

Section 3
Inter-port
Test

Port 2
Port m

(a)
Port 1

Single-port
Test Algorithm

Port 2

Multi-port
AF Test

Inter-port
MPF Test

Port m

(b)

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Dual-Port RAM Test

Port 1

Port 2

r0 w

- -

Section 1
r1w 0 r0 w 1r1 r1w 0r0

r0

r0 w

- -

- - -

- - -

Section 2
r1w 0

- -

- -

- -

r0 w

Section 2
r1w 0

- -

- -

r0 w

Section 3
r0 w 1 r1w

- 1

r1w

r 1r
N

r 0r
N

(a)
Port 1

Port 2

r0 w
r 1r
N

1
S

Section 1
r1w 0 r0 w 1r1 r1w 0r0

r0

r0 w

r 0r

- -

- - -

- - -

- 1

r1w

Section 3
(b)

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0
S

Compacted Dual-Port RAM Test

Port 1

Port 2

r0 w
r 1r
N

1
S

Section 1
r1w 0

- - r

r 0r

r0 w

- - r
r1w

Section 2
(c)
Port 1

Port 2

r0 w
r 1r
N

1
S

r1w
r 0r
N

0
S

- r0 w

- 1

* Time complexity: 10N

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r1w

r
0

(d)

47

Four-Port RAM Test

AF Test
Port 1

Port 2

r N1 r S0

r N0 r

r0 w

Port 3

r N1 r S0

r N0 r

r S1 r N 0

r S0 r N1 r 0 w

Port 4

r N1 r S0

r N0 r

r S1 r N 0

r S0 r N1 r N1 r S0

r0 w

r 1w

- -

- 1

r 1w

- -

- -

- -

- -

- -

- -

- -

- -

- -

- -

r 1w

r N 0 r S1 r 0 w

r 1w

Inter-port Test

* Time complexity: 17N

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Testing 6-Read-1-Write RAM

M0

M1

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

M2

M3
w

r N0 r

r N0 r

0
N

Test for ports of

distance 1

* Time complexity: 13N

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M4
w

M5

r N0

r N0 -

r N0

r N0 -

r N0

r N0 -

r N0

r N0 -

r N0

r N0

0
S

Test for ports of

distance 2

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M6
w

Test for ports of

distance 3

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Flash Memory Testing

Testing nonvolatile memories:

Masked ROM---exhaustive; pseudorandom

PROM (OTP) & EPROM---dummy row
EEPROM & flash memory---dummy row?

Testing flash memory core is hard

Customized core and I/O
Isolation (accessibility)

Reliability issues: disturbances, over

program/erase, under program/erase, data

retention, cell endurance, etc.
Long program/erase time
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Flash Memory Overview

Flash memory can be programmed and erased
electrically
Has the advantages of EPROM and EEPROM

A stacked gate transistor with both the control

gate (CG) and floating gate (FG):
Control gate

Floating gate
Drain

Source

n+

n+

P-Si

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D
G
S

51

Flash Memory Program & Erase

Program(1 to 0): channel hot-electron (CHE) injection or FowlerNordheim (FN) electron tunneling
Erase (0 to 1): FN electron tunneling
By the entire chip or large blocks (flash erasure)
Different products have different program/erase mechanisms

Program
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Erase
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Flash Memory Cell Types

Stacked-gate

Split-gate

Select-gate

Operations: Read, Program, Erase (Flash Erase)

As opposed to Read and Write in RAM

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Programming Scheme Comparison

CHE Injection

Channel FN Tunneling

High power (dual

external supplies)

Low power (single

external supply)

Low oxide field stress

High oxide field stress

Faster program
Slower program
operation (byte program operation (improved by
limited by power)
page program)

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NOR-Array Structure

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NAND-Array Structure
Select (drain)
WL 1
WL 2
WL 3
WL 4

WL 16
Select (source)

BL i

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56

Disturbance Example (I)

Program Disturbance
BL0

SL

WL0

BL1

BL2

SL

BL3

0V
0V
6V
Drain-Disturb on "Programmed Cell"
10V
10V

WL1
0V

0V

6V
Programming

10V

0V
0V
Gate-Disturb on "Erased Cell"

WL2

NOR-Type Common Ground Standard (Stacked Gate)

mbist1.10

Cheng-Wen Wu, NT

57

Disturbance Example (II)

Read Disturbance
BL0

SL

BL1

BL2

SL

BL3

WL0

WL1

5V
0V
1V
Soft-Program on "Selected Cell"

WL2

mbist1.10

Cheng-Wen Wu, NT

58

Disturbance Example (III)

Program Disturbance

BL0
SSL

BL1
3.3V

3.3V

3.3V

BL2
0V

Gate-Disturb on "Erased Cell"

0V
WL 0

10V
2.8V

WL 1

0V

18V

18V
Program '1'

Program '0'

2.8V
WL 2

GSL

mbist1.10

10V

0V
10V

2.8V
0V
Gate-Disturb on "Programmed Cell"
0V
0V

Cheng-Wen Wu, NT

59

Disturbance Example (IV)

Read Disturbance
BL0

BL1

Erase Disturbance
BL2
0.7V

5V
5V

BL0

SSL

5V

WL0

5V

5V

WL 0

21V

0V

21V

0V

21V

WL1

0V

0V

WL 1

21V

0V

21V

0V

21V

WL 2

21V

0V

21V

0V

21V

Vth=+2V

Floating

Floating

Vth=-3V

WL2

5V

5V

GSL

5V

5V

mbist1.10

SSL

BL2

BL1

soft-program

GSL

Cheng-Wen Wu, NT

Floating

Floating

60

Gate Program Disturb Fault (GPDF)

Conditions:

1.Victim cell initial value is a logic 1

2.Aggressor 10 (program)

Control Gate

Floating Gate

Source

D
Drain

Victim 10 (program)
V(L)

V(H)
V(H)

Substrate

V(L)

V(Gd)

mbist1.10

Cheng-Wen Wu, NT

61

Gate Erase Disturb Fault (GEDF)

Conditions:

1.Victim cell initial value is a logic 0

2.Aggressor 10 (program)

Control Gate

Floating Gate

Source

Victim 01 (erase)
V(L)

Drain

V(H)
V(H)

Substrate
V(L)

B
V(Gd)

mbist1.10

Cheng-Wen Wu, NT

62

Drain Program Disturb Fault (DPDF)

Conditions:
1.Victim cell initial value is a logic 1
2.Aggressor 10 (program) Victim 10 (program)
V(H)
During programming, erased cells on
unselected rows on a bit-line that is being
programmed may have a fairly deep
depletion region formed under them

V(H)

Electrons entering this depletion region can

be accelerated by the electric field and
injected over the oxide potential barrier to
adjacent floating gates

V(L)

mbist1.10

Cheng-Wen Wu, NT

V(Gd)

63

Drain Erase Disturb Fault (DEDF)

Conditions:
1.Victim cell initial value is a logic 0

2.Aggressor 10 (program)
Victim 01 (erase)

Control Gate

Floating Gate

Source

V(L)

Drain

V(H)
V(H)

Substrate
V(L)

B
V(Gd)

mbist1.10

Cheng-Wen Wu, NT

64

Read Disturb Fault (RDF)

Conditions:
1. Occurs on the selected cell

2. Cell initial value is logic 1

Control Gate

Floating Gate

Source

D
Drain

Substrate

mbist1.10

Soft-Program
During the read operation,
hot carriers can be injected
from the channel into the FG
even if at low gate voltages

Cheng-Wen Wu, NT

65

Over Erase Fault (OEF)

Flash memory erase mechanism is not
self-limiting
Threshold voltage can be low enough to
turn the cell into a depletion-mode
transistor
Fault behavior:

An unselected cell in the same bit-line has

excessive source-drain leakage current

Reading that cell leads to incorrect value
(like DEDF)
Cannot be programmed correctly (like TF)
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Cheng-Wen Wu, NT

66

Basic RAM Faults for Flash Memory

Address-Decoder Fault (AF)
Stuck-At Fault (SAF)
Transition Fault (TF)
Stuck-Open Fault (SOF)
Bridging Fault (BF)
Coupling faults need not be considered!
Replaced by disturb faults

mbist1.10

Cheng-Wen Wu, NT

67

Reliability Consideration
Reliability characteristics of floating-gate
ICs depend on
Circuit density, circuit design, and process

integrity
Memory array type and cell structure

Reliability stressing and testing must then

be oriented toward determining the relevant
failure rates for the particular array under
consideration
mbist1.10

Cheng-Wen Wu, NT

68

Data Retention Fault

Retention time: the time from data storage to the
time at which a verifiable error is detected from
any cause
Intrinsic retention times exceed millions of years in

the operating temperature range

Months at 300C
1 million years at 150 C
120 million years at 55 C

Data Retention Fault (DRF)

Static leakage

Built-in data retention test circuit

mbist1.10

Cheng-Wen Wu, NT

69

Cell Endurance Fault

Endurance: a measure of the ability to meet datasheet specifications as a function of accumulated
program/erase cycles
Endurance limit is a result of damage to the

dielectric around the floating gate caused by

electric stresses
In many flash devices, the end of endurance is
generally caused by hot electron trapping in the
charge transport oxide

Cell Endurance Fault (CEF)

Threshold window shift due to increased

program/erase cycles
Built-in stress test circuit
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Cheng-Wen Wu, NT

70

Composite Failure Rate Determination

125C dynamic life stress
The 125C dynamic life stress is the standard

MOS memory continuous dynamic read in a burnin chamber

Endurance test
The endurance test is the repeated data

complementing of floating-gate devices, possibly at

temperature extremes

Extended data retention stress

This test is constituted by a high-temperature bake

with a charge polarity that is opposite to the

equilibrium state on the floating gate

mbist1.10

Cheng-Wen Wu, NT

71

Typical Test Modes (Characterization)

Stress (row/column)

Reverse tunneling stress

Punch through stress
Tox stress
DC stress

Mass program
Weak erase
Leak (thin-oxide, bit-line, etc.)
Cell current; cell Vt
Margin
Etc.
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72

Test Patterns
A RAM test pattern definition includes both the
data pattern and the address pattern
The time to read a pattern is the same as the time

to write a pattern

For flash memories, however, the address and

data pattern definitions must be segregated
It has long write times relative to the read times

Typical data patterns:

Solid, checkerboard, random, etc.

Typical address patterns:

Address increment/decrement, address

complement, column/diagonal galloping, etc.

mbist1.10

Cheng-Wen Wu, NT

73

Testing GPDF
Flash
Program the first column
Read all cells except the first column
Flash
Program any column except the first
Read the first column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000

mbist1.10

Cheng-Wen Wu, NT

74

Testing GEDF
Flash
Program all cells
Read all cells except the last column
Program any column except the last
Read the last column
*Assume reading and programming are done column-wise
Source: Saluja, et al., Int. Conf. VLSI Design, 2000

mbist1.10

Cheng-Wen Wu, NT

75

Test Coverage: Previous Results

Fault

DCP

DCE

DD

EF

GF

SAF

50%

50%

50%

100%

100%

TF

12.5%

50%

50%

87.5%

62.5%

AF

40%

0%

0%

44.5%

40%

SOF

0%

0%

0%

12.5%

6.2%

CFst

25%

25%

25%

50%

50%

GPDF

33.3%

0%

0%

100%

33.3%

GEDF

0%

100%

75%

100%

100%

DEDF

0%

75%

100%

100%

100%

DPDF

0%

0%

0%

0%

0%

Source: Saluja, et al., Int. Conf. VLSI Design, 2000

mbist1.10

Cheng-Wen Wu, NT

76

March-Based Flash Test: March-FT

{(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)}
This Flash memory is NOR type (Stacked gate).
Memory size (N) : 65536
Test length : 2(chip erase time) + 131072(word program time) + 393216(word read time)
Test time : 7.207173 sec
SAF : 100%
(131072 / 131072)

P.S.

TF : 100%

(131072 / 131072)

Flash Type = NOR

SOF : 100%

(65536 / 65536)

Gate Type = Stack

AF : 100%

(4294901760 / 4294901760)

Row Number = 256

CFst : 100%

(17179607040 / 17179607040)

Col Number = 256

GPD : 100%

(16711680 / 16711680)

Word Length = 1

GED : 100%

(16711680 / 16711680)

Chip erase time = 3 sec

DPD : 100%

(16711680 / 16711680)

Word program time = 9u sec

DED : 100%

(16711680 / 16711680)

Word read time = 70n sec

RD : 100%

(65536 / 65536)

OE : 100%

(65536 / 65536)

mbist1.10

Cheng-Wen Wu, NT

77

Test Length (Bit-Oriented)

Notation:

F : Flash time
P : Program time
R : Read time
r : row number

c : column number

mbist1.10

DCP 2(F) + 2r(P) + rc(R)

DCE (F) + (c+1)r(P) + rc(R)
DD

(F) + (r+1)c(P) + rc(R)

EF

2(F) + (rc+2r+c-2)(P) +
(2rc+r+c-3)(R)

GF

2(F) + (rc+2r+c-1)(P) +
(2rc+c+r-2)(R)

FT

2(F) + 2rc(P) + 6rc(R)

Cheng-Wen Wu, NT

78

Test Length (Word-Oriented)

Word length = w:

2(F)+2rc(P)+6rc(R)+log(w)[2(F)+rc(P)+rc(R)]

solid background

standard background

testing time

testing time

Solid: 0000 (1111)

Standard: 0101 (1010), 0011 (1100)

Ex: word length w = 4

6(F) + 4rc(P) + 8rc(R)

mbist1.10

Cheng-Wen Wu, NT

79

Test Algorithm Generation by Simulation (TAGS)

T(N) Test algorithms
(f); (r1)
2N
3N

(f); (w0); (r0)

4N

(f); (r1,w0); (r0)

5N

(f); (r1,w0,r0); (r0)

6N

(f); (r1,w0,r0); (r0,w0)

7N
8N
9N

(f); (r0); (r1,w0,r0); (r0,w0)

(f); (r1,w0); (f); (r1,w0,r0); (r0)
(f); (r1,w0); (r0); (f); (r1,w0,r0); (r0)
(f); (r1,w0,r0); (r0); (f); (r1,w0,r0); (r0)

10N
mbist1.10

Cheng-Wen Wu, NT

80

Embedded Memory Testing

Memories are one of the most universal cores
In Alpha 21264, cache RAMs represent 2/3
transistors and 1/3 area; in StrongArm SA110, the
embedded RAMs occupy 90% area [Bhavsar, ITC-99]
In average SOC, memory cores will represent more

than 90% of the chip area by 2010 [ITRS 2000]

Embedded memory testing is increasingly difficult

High bandwidth (speed and I/O data width)

Heterogeneity and plurality

Isolation (accessibility)
AC test, diagnostics, and repair

BIST is considered the best solution

mbist1.10

Cheng-Wen Wu, NT

81

Embedded RAM Test Support

Test run
Isolation only Isolation & BIST
Probe test
Tester
Tester/BIST
Pre-BI test
Tester
BIST
BI
BI board
BIST
Post-BI test
Tester
BIST
Final test
Tester
Tester/BIST

mbist1.10

Cheng-Wen Wu, NT

82

RAM BIST Approaches

Methodology

Processor-based BIST
Programmable
Hardwired BIST
Fast
Compact

Interface

Serial (scan, 1149.1)

Parallel (embedded controller; hierarchical)

Patterns (address sequence)

March
Pseudorandom

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Cheng-Wen Wu, NT

83

Typical RAM BIST Architecture

Controller
Test Collar (MUX)

Pattern
Generator

Go/No-Go

RAM

Comparator
BIST Module
RAM Controller

mbist1.10

Cheng-Wen Wu, NT

84

Serial March (SMarch)

{ ( rxw0) c (r 0 w0) c ; ( r 0 w1) c ( r1w1) c ; (r1w0) c (r 0 w0) c ;
(r 0 w1) c (r1w1) c ; (r1w0) c (r 0 w0) c ; ( r 0 w0) c ( r 0 w0) c }
From March C-

Serial interface

One BIST for all

(cascaded)

One-bit read/write at a
time, but one pattern
Addr
per cycle

Slow

No diagnostics

SI

X Decoder

Memory Cell Array

Y Decoder

Transparent Serial Data-MUX

c

SO

Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990

mbist1.10

Cheng-Wen Wu, NT

85

Syntest MBIST

Algorithms:
March C MOVI
March C++
Checkerboard

FSM

Shared controller for

multiple RAMs
Synthesizable RTL
code
Pass
BistFail

CE
OE
WEB

ADR Control

Data Generator

Analyzer

Finish
Source: Syntest

mbist1.10

Cheng-Wen Wu, NT

86

NTHU/GUC EDO DRAM BIST

mbist1.10

Cheng-Wen Wu, NT

87

DRAM Page-Mode Read-Write Cycle

mbist1.10

Cheng-Wen Wu, NT

88

Programmable Memory BIST

(PMBIST)

mbist1.10

Cheng-Wen Wu, NT

89

PMBIST Architecture

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Cheng-Wen Wu, NT

90

Controller and Sequencer

Controller

Microprogram
Hardwired

Shared CPU core

IEEE 1149.1 TAP

Sequencer (Pattern Generator)

Counter
LFSR
LUT

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Cheng-Wen Wu, NT

91

Controller

mbist1.10

Cheng-Wen Wu, NT

92

Sequencer

BIST
Controller

Combination Logic #0
Combination Logic #1
Row Address Counter
Column Address
Counter
Control Counter

State

eDRAM

eDRAM
control
signal

Flags
MCK

MCK
Comparator

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Cheng-Wen Wu, NT

93

PMBIST Test Modes

1. Scan-Test Mode
2. RAM-BIST Mode
1.Functional faults
2.Timing faults (setup/hold times, rise/fall times,

etc.)
3.Data retention faults

3. RAM-Diagnosis Mode
4. RAM-BI Mode
mbist1.10

Cheng-Wen Wu, NT

94

PMBIST Controller Commands

Bit 4
Bit 3
Bit 2, Bit 1, Bit 0
Addressing order Data type
Operations
000: EOT
(End of test)
1: (increasing) 1: d = DB
(READ Cycle)
0: (decreasing) 0: d = ~DB 001: Rd
010: Wd
(Early WRITE Cycle)
011: RdW~d
(READ-WRITE) Cycle
EDO-PAGE-MODE
100: Wd
(Early WRITE Cycle
101: RdW~d
(READ-WRITE) Cycle
110: RdW~dR~d (READ Early WRITE Cycle)
111: Refresh

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Cheng-Wen Wu, NT

95

PMBIST Control Sequence

mbist1.10

Cheng-Wen Wu, NT

96

BIST Area Overhead

3%

Overhead
Mem size
0.3%

mbist1.10

Cheng-Wen Wu, NT

97

Processor-Based RAM BIST

Processor

mbist1.10

Cheng-Wen Wu, NT

98

On-Chip Processor-Based RAM BIST

BIST program is stored in boot ROM during
design phase, and memory BIST is done by
executing BIST program
Address
bus

DATAI
bus

DATAO
bus

Control
bus

BOOT
ROM
Embedded
memory
CPU core

I/O port

mbist1.10

Cheng-Wen Wu, NT

99

Testing RAM Core by On-Chip CPU

6502 assembly program that performs March Ctest algorithm
data background

M0:

M1:

mbist1.10

.org
LDX
LDA

0HFF00
#$$00
#$$55

STA
INX
CPX
BNE
LDX

0000,X

(W0)

#$$FF
M0
#$$00

(R0W1)

LDA
CMP
BNE
LDA
STA
INX
CPX
BNE
LDX
. . . .

0000,X
#$$55
ERROR
#$$AA
0000,X

(R0W1)

#$$FF
M1
#$$00
.

write data background to memory

March C- algorithm

(R1W0)
(R1W0)
(R0)
read from memory
write data background to memory

Cheng-Wen Wu, NT

100

Test Speed Consideration

Processor-BIST speed is lower than dedicated
BIST circuit
Total clock cycles to implement MARCH C- is
O(114N)
Table 1. 6502 instruction cycles
IMM

ABX

IMP

REL

LDA

LDX

STA

INX

CPX

BNE

2~4

CMP

mbist1.10

Cheng-Wen Wu, NT

101

NTHU Processor-Programmable BIST

A D D R _cpu
0

ADDR

D A TA O _cpu
0

clock_cpu

B IST core

m ux_sel

ctrl_bist
1

ctrl_cpu

D A TA I_bist

D A TA I_sys

DI

em bedded
m em ory
control

D A TA I_cpu

control

on-chip bus

em bedded
C PU

A D D R _bist
D A TA O _bist

D A TA O

D A TA I
DO

B IST circuitry
m ux_sel= 0 in norm alm ode
m ux_sel= 1 in B IST m ode

mbist1.10

Cheng-Wen Wu, NT

I/O circuitry

102

Advantages and Disadvantages

Advantages
Reuse of on-chip CPU core
Might need modification
Core March elements can be implemented in

hardware, allowing different March algorithms to be

executed via assembly programming

Disadvantages
Some address space will be occupied by PPBIST
Area overhead

mbist1.10

Cheng-Wen Wu, NT

103

PPBIST Implementation

D A TA O _cpu
D A TA O _bist

R BG
A D D R _cpu

low est/highestaddress

RAL
address
decoder

RAH

R EA

RM E

R FLA G

R IR

R ED

address counter
up /dow n
controller

A D D R _bist
read /w rite
control

m atch /unm atch

D A TA I_bist

com parator

D A TA I_sys

data background

mbist1.10

Cheng-Wen Wu, NT

104

PPBIST Data Registers

Register

Function

RBG

Store background data

RAL

Store lowest address

RAH

Store highest address

RME

Store current March element

RIR

Instruction register

RFLAG

Status register

RED

Erroneous response of defective memory cell

REA

Address of defective memory cell

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Cheng-Wen Wu, NT

105

PPBIST Test Procedure

CPU write data back ground
CPU write start/stop address
CPU write MARCH element instruction
CPU write START instruction to wrapper

BIST core
(W0)

BIST core
(R0W1)

BIST core
(R1W0)

BIST core
(R0W1)

compare error?

BIST core
(R1W0)
yes

no
complete?
yes
write complete flag

mbist1.10

Cheng-Wen Wu, NT

BIST core
(R0)

write error flag

write faulty address
write faulty data

no

CPU take over

106

PPBIST Example Using 6502

6502 assembly program that performs March Ctest algorithm under the proposed BIST scheme
START: LDA
STA
LDA
STA
LDA
STA
LDA
STA
LDA
STA
M0:
LDA
STA
JSR
M1:
LDA
. . . . . .

mbist1.10

#$$55
0HFFE0
#$$00
0HFFE1
#$$00
0HFFE2
#$$FF
0HFFE3
#$$0F
0HFFE4
#$$00
0HFFE5
BIST
#$$01

END:

LDA
STA
JMP

#$$04
0HFFE6
FINISH

BIST:

LDA
STA
LDA
CMP
BEQ
CMP
BNE
RTS

#$$00
0HFFE6
0HFFE7
#$$01
ERROR
#$$FF
LOOP

ERROR: LDA
STA
JMP

#$$03
0HFFEA
FINISH

LOOP:

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107

PPBIST Example
Addresses of the registers in the BIST experiment
Register

Address

Register

Address

RBG

FFE0

RIR

FFE6

RAL

FFE1 ~ FFE2

RFLAG

FFE7

RAH

FFE3 ~ FFE4

RED

FFE8

RME

FFE5

REA

FFE9 ~ FFEA

March elements and the corresponding RME

M0

M1

M2

M3

M4

M5

0H

1H

2H

3H

4H

5H

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Cheng-Wen Wu, NT

108

Experimental Results
Total test time in terms of clock cycles
The sum of all the March elements' test time plus

30 clock cycles

10N clock cycles to perform March C-

Test time of each March element :

M0

M1

M2

M3

M4

M5

1N

2N

2N

2N

2N

1N

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109

Comparison of BIST Methodologies

BIST scheme

Test time H/W overhead

Routing overhead

Integrated BIST core

Short

Low

High

On-chip processor

Very long Zero

Zero

Ours

Short

zero

mbist1.10

Very low

Cheng-Wen Wu, NT

110

RAM BIST Compiler

Use of RAM cores is increasing.
SRAM, DRAM, flash RAM
Multiple cores

RAM BIST compiler is the trend.

BRAINS (BIST for RAM in Seconds)
Proposed BIST Architecture
Memory Modeling
Command Sequence Generation
Configuration of the Proposed BIST

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111

BRAINS Outputs
Synthesizable BIST design

At-speed testing
Programmable March algorithms
Optional diagnosis support
BISD

Activation sequence
Test bench
Synthesis script
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112

BIST Synthesis Flow

GUI

RAM/BIST
Description
Parser

Memory
Library

Compile
Engine

BIST
Template

mbist1.10

RTL
Synthesis

Netlist

Cell
Library

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113

NTHU/GUC PMBIST Architecture

Programmable Memory BIST

Controller

MSO
MRD
MBO

Sequencer

TPG
Controls

Test Collar

MCK
MBS
MBC
MBR
MSI

Comparator

Address
D

Memory

Q
Normal
Access

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114

PMBIST with Scan

Test Command/Information Storage
Module

Serial
data in

Memory
Command

Command

BIST
control
signals

Controller

Handshaking

Error

Serial
data out

Sequencer

Address

Test
Pattern
Generator

To
Memory

Error

Source: Cheng, et al., DFT00

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115

Sequencer
Address Generator
Control
Module

Sequence Generator

go
Command Generator
error
info.

Error Handling Module

mbist1.10

address

Cheng-Wen Wu, NT

command
error
signature

116

State Diagram of Control Module

BIST
idle
BIST
idle
BIST
active

BIST
done
BIST
done

BIST
apply

For SRAM
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Cheng-Wen Wu, NT

BIST
apply
For DRAM
117

DRAM Page-Mode Operation

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118

Memory Specification Techniques

Memory Specifications
I/O Specification
Command Specification
Task Specification
Delay Constraint Specification
AC Parameter Specification

Support customized memories.

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119

I/O Specification
Four parameters
IO_type
IO_width
IO_latency
IO_packet_length

IO_type: input, output, or inout

IO_width: port width (#bits), can be a constant
or specified by user

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I/O Specification
IO_latency: port latency

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I/O Modeling
IO_packet_length: #bits packed within a clock
cycle for the port

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Command Specification
Specifies the memorys instructions

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Task Specification
Specifies a complete memory operation
A task can be a single command or a sequence
of commands.

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Delay Constraint Specification

Specifies the minimal time interval between any
two tasks

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AC Parameter Specification
Specifies input and output delays
Specified parameters will be inserted into the
synthesis script.

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Memory Specification Example

For ZBT SRAM:
Method A:
@latency D = 1;
@task write = {write};
Method B:
@latency D = 0;
@task write = {pre_write, post_write};

The BIST circuit from method A is faster than

the one from method B, but it has higher area
overhead
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Sequence Generation
For each March element, the compiler generates
the command sequence according to the read
task, write task, and minimum delay between the
two tasks
For example:

task read = {A}

task write = {B, C}
minimum delay between read and write = 10ns
clock period = 10 ns
Then the (rw) element becomes {A, nop, B, C}

One can also optimize the command sequence

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Fast Access Mode

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Diagnosis Support
The BIST circuit scans out the error information
(element, address, signature, and polarity) during
the diagnosis mode.
Assume address 20h stuck-at 64h:

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Multiple RAM Cores

Controller and sequencer can be shared.
Test pattern
generator

Ram Core A

Test pattern
generator

Ram Core B

Test pattern
generator

Ram Core C

sequencer
controller

sequencer

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Experimental Results
The Built-In Memory List

DRAM
EDO DRAM
SDRAM
DDR SDRAM
SRAM
Single-Port Synchronous SRAM
Single-Port Asynchronous SRAM
Two-Port Synchronous Register File
Dual-Port Synchronous SRAM
Micron ZBT SRAM

BRAINS can support new memory architecture

easily
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Experimental Results

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Experimental Results
Four single-port SRAM BIST circuits share the same controller and
sequencer.
Size of the SRAM core: 8K x 16

Original
BIST area for single-port
SRAM: 1438 (gates)
Total area = 1438 * 4 =
5752 (gates)

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Shared
gate count: 3350

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Experimental Results
8K x 16 single-port synchronous SRAM (0.25um)
Area:

Die size: 1780.74 x 755.07 um2

BIST area: 80.1 x 583.48 um2
Area overhead : 3.4%

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Experimental Results
2K x 32 two-port register file (0.25um)
Die size: 1130.74 x 936.34 um2
BIST area: 77.88 x 620 um2
Area overhead: 4.5%

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Why RAM Diagnostics?

Memory testing is more and more important

Memories are key components

Represent about 30% of the semiconductor market
Dominate the chip area/yield

Memory testing is more and more difficult

Growing density, capacity, and speed
Emerging new architectures & technologies
Growing need for embedded memories

Why diagnostics?
Yield improvement

Repair and/or design/process debugging

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Fault Model Subtypes

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NTHU-FTC BIST Architecture

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Test Mode
In Test Mode it runs a fixed algorithm for
production test and repair

Only a few pins need to be controlled, and BGO

reports the result (Go/No-Go)

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Fault Analysis Mode

In Fault Analysis Mode, we can apply a longer
March algorithm for diagnosis

FSI captures the error information of the faulty cells

EOP format:

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Error Catch and Analysis

Locate the faulty cells

Identify the fault types

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How to Identify Fault Type?

RAM Circuit/Layout

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Tester/BIST Output

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March Dictionary
March 11N
E0

E1 E2

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E4 E5

E6 E7

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E10

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March Signature and Error Map

March Signature (Syndrome)

Error Map

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MECA System

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Error Analyzer
Tester/BIST data log

Data log parser

Error maps
March
Dictionary

Fault analysis

Fault maps
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Fault Analysis
Derive analysis equations from the fault dictionary

Convert error maps to fault maps by the

equations

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Test Algorithm Generation

Start from a base test: generated by TAGS or

user-specified
Generation options reduced to read-insertions

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Diagnostic Resolution
Diagnostic resolution
# of distinguishable faults
Diagnostic resolution
# of detectable faults

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Experimental Results
Proposed diagnosis framework has been
applied to commercial embedded SRAMs
Results for a 16Kx8 embedded SRAM
(FS80A020) are shown
Tester log from Credence SC212 is examined
Address remapping (logical to physical) is
applied

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The Total Error Bitmap

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Fault Bitmaps
Idempotent Coupling Fault

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Redundancy and Repair

Problem: We keep shrinking the feature size and
increasing the chip density and size. How do we
maintain the yield?
Solutions:

Fabrication
Material, process, equipment, etc.
Design
Device, circuit, etc.
Redundancy and repair
On-line

EDAC (extended Hamming code; product code)

Off-line

Spare rows and/or columns

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From BIST to BISR

BIST

BISD

BIRA

BISR

BIST: built-in self-test

BIECA: built-in error catch & analysis
-BISD: built-in self diagnosis
-BIRA: built-in redundancy analysis

BISR: built-in self-repair

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RAM Built-In Self-Repair (BISR)

Reconfiguration Mechanism

Analyzer
MUX

RAM

BIST

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Redundancy

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RAM Redundancy
1-D: spare rows (or columns) only
SRAM
Algorithm: Must-Repair

2-D: spare rows and columns

Local and/or global spares
NP-complete problem
Conventional algorithm:
Must-Repair phase
Final-Repair phase

Repair-Most (greedy) [Tarr et al., 1984]

Fault-Driven (exhaustive, slow) [Day, 1985]
Fault-Line Covering (b&b) [Huang et al., 1990]

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Redundancy Architectures

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An SRAM with BISR

[Kim et al., ITC 98]

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A DRAM Redundancy Example

4 local spare rows per block

2x4=8 global spare columns

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Definitions
Faulty line: row or column with at least one faulty
cell.
A faulty line is covered if all faulty cells in the line
are repaired by spare rows and/or columns.
A faulty cell not sharing any row or column with
any other faulty cell is an orthogonal faulty cell.
r: number of (available) spare rows
c: number of (available) spare columns
F: number of faulty cells in a block
F:number of orthogonal faulty cells in a block
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Example Block with Faulty Cells

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Repair-Most (RM)
Run

BIST and construct

bitmap.
Construct row and column
error counters.
Run Must-Repair algorithm.
Run greedy Final-Repair
algorithm.

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Worst-Case Bitmap (After MustRepair)

Max F=2rc.
Max F=r+c.
Bitmap size: (rc+c)(cr+r).

r=2; c=4

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Local Repair-Most (LRM)

RM is not good enough for embedded RAM.

Large storage requirement: bitmap and counters

Slow

LRM improves the performance.

Repair-Most based
Improved heuristics
Early termination rules
Concurrent BIST and BIRA
No separate Must-Repair phase

LRM reduces the storage required.

Smaller local bitmap
From (rc+c)x(cr+r) to mxn

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LRM Algorithm
Activated by BIST whenever a faulty cell is
detected.
Fault Collection (FC)
Collects faulty-cell addresses.
Constructs local bitmap.
Counts row and column errors.

Spare Allocation (SA)

Allocate spare rows or columns when bitmap is full.
Allocate spare rows or columns at end.

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LRM: FC and SA

(1,0), (1,6), (2,4), (3,4), (5,1), (5,2)

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LRM Example

(5,2)

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Local Optimization (LO)

LMR has drawbacks:

Selecting line with largest fault count may be slow.

Multiple lines may need to be selected for repair.
Area overhead is still high.
Repair rate depends on bitmap size.

LO has a better repair rate based on same

hardware overhead, i.e., a higher repair
efficiency.

Fault Collection (FC)

Records faulty cells in bitmap until it is full.
Spare Allocation (SA)
Exhaustive search performed for repairing all faults.
Bitmap cleared; process repeated until done.

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LO: Column*/Row Selection for SA

A 1 means that the corresponding

col is selected for repair, unless empty.

Col selection vector

Row selection vector

1. Col 5 selected for repair.

2. Row 5 is selected for repair.

* Assume column selection has a lower cost than row selection.

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LO Example

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Essential Spare Pivoting (ESP)

Maintain high repair rate without using a bitmap.
Small area overhead.

Fault Collection (FC)

Collect and store faulty-cell address using row-

pivot and column-pivot registers.

If there is a match for row (col) pivot, the pivot is an

essential pivot.
If there is no match, store the row/col addresses in
the pivot registers.

If F > r+c, the RAM is unrepairable.

Spare Allocation (SA)

Use row and column pivots for spare allocation.

Spare rows (cols) for essential row (col) pivots.
SA for orthogonal faults.

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ESP Example

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Cell Fault Size Distribution

Mixed Poisson-exponential distribution.

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Repair Rate Comparison

1,552 RAM blocks.

1,024x64 bits per block.
r from 6 to 10.
c from 2 to 6.
LRM bitmap: rxc.
LO bitmap: 8x4.

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Normalized Repair Rate

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Repair Rate (r=10)

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Normalized Repair Rate (r=6)

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Area Overhead

Overhead is about 5-12% for 16Mb DRAM, r=8, and c=4.

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Computation Time (Simulated)

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