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William Stallings Computer Organization and Architecture 7th Edition Internal Memory

This document discusses different types of computer memory. It describes dynamic RAM (DRAM) which uses capacitors to store bits and must be regularly refreshed. Static RAM (SRAM) uses flip-flops and does not require refreshing. Read-only memory (ROM) permanently stores data and is non-volatile. Synchronous DRAM (SDRAM) provides data in sync with the system clock, allowing the CPU to do other tasks while waiting. Error correction codes can detect and fix soft errors in memory without permanent damage.

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136 views

William Stallings Computer Organization and Architecture 7th Edition Internal Memory

This document discusses different types of computer memory. It describes dynamic RAM (DRAM) which uses capacitors to store bits and must be regularly refreshed. Static RAM (SRAM) uses flip-flops and does not require refreshing. Read-only memory (ROM) permanently stores data and is non-volatile. Synchronous DRAM (SDRAM) provides data in sync with the system clock, allowing the CPU to do other tasks while waiting. Error correction codes can detect and fix soft errors in memory without permanent damage.

Uploaded by

Malik Hassan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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William Stallings

Computer Organization
and Architecture
7th Edition
Chapter 5
Internal Memory
http://www.cs.uncc.edu/~abw/ITCS3182S06/index.ht
ml

Semiconductor Memory Types

Semiconductor Memory
RAM

Misnamed as all semiconductor memory is


random access
Read/Write
Volatile
Temporary storage
Static or dynamic

Dynamic RAM

Bits stored as charge in


capacitors
Charges leak
Need refreshing even when
powered
Simpler construction
Smaller per bit
Less expensive
Need refresh circuits
Slower
Main memory
Essentially analogue

Level of charge determines value

DRAM Operation
Address

line active when bit read or written

Transistor switch closed (current flows)

Write

Voltage to bit line


High for 1 low for 0

Then signal address line


Transfers charge to capacitor

Read

Address line selected


transistor turns on

Charge from capacitor fed via bit line to sense


amplifier
Compares with reference value to determine 0 or 1

Capacitor charge must be restored

Static RAM
Bits

stored as on/off switches


No charges to leak
No refreshing needed when powered
More complex construction
Larger per bit
More expensive
Does not need refresh circuits
Faster
Cache
Digital

Uses flip-flops

Stating RAM Structure

Static RAM Operation


Transistor

arrangement gives stable logic

state
State 1

C1 high, C2 low
T1 T4 off, T2 T3 on

State

C2 high, C1 low

T2 T3 off, T1 T4 on

Address
Write

line transistors T5 T6 is switch

apply value to B & compliment to B


Read value is on line B

SRAM vs DRAM
Both

volatile

Power needed to preserve data

Dynamic

Simpler to build, smaller


More dense
Less expensive
Needs refresh
Larger memory units

Static

cell

Faster
Cache

Read Only Memory (ROM)


Permanent

storage

Nonvolatile

Microprogramming
Library

(see later)

subroutines
Systems programs (BIOS)
Function tables

Types of ROM
Written

during manufacture

Very expensive for small runs

Programmable

PROM
Needs special equipment to program

Read

(once)

mostly

Erasable Programmable (EPROM)


Erased by UV

Electrically Erasable (EEPROM)


Takes much longer to write than read

Flash memory
Erase whole memory electrically

Organisation in detail
A

16Mbit chip can be organised as 1M of


16 bit words
A bit per chip system has 16 lots of 1Mbit
chip with bit 1 of each word in chip 1 and
so on
A 16Mbit chip can be organised as a 2048
x 2048 x 4bit array

Reduces number of address pins


Multiplex row address and column address
11 pins to address (211=2048)
Adding one more pin doubles range of values so x4
capacity (212 x4 Capacity with 211)

Refreshing
Refresh

circuit included on chip


Disable chip
Count through rows
Read & Write back
Takes time
Slows down apparent performance

Typical 16 Mb DRAM (4M x 4)

Packaging

Module
Organisation
256Kbit

per Chip
8 chips to
construct 256KB

Module Organisation (2)

Error Correction

Hard Failure

Soft Error

Permanent defect
Random, non-destructive
No permanent damage to memory

Detected using Hamming error correcting code

Error Correcting Code Function

Advanced DRAM Organization


Basic

DRAM same since first RAM chips


Enhanced DRAM

Contains small SRAM as well


SRAM holds last line read (c.f. Cache!)

Cache

DRAM

Larger SRAM component


Use as cache or serial buffer

Synchronous DRAM (SDRAM)

Access is synchronized with an external clock


Address is presented to RAM
RAM finds data (CPU waits in conventional DRAM)
Since SDRAM moves data in time with system clock,
CPU knows when data will be ready
CPU does not have to wait, it can do something else
Burst mode allows SDRAM to set up stream of data
and fire it out in block
DDR-SDRAM sends data twice per clock cycle
(leading & trailing edge)

IBM 64Mb SDRAM

SDRAM Operation

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