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Unit2 - MOS Scaling and Packaging

This document discusses VLSI technology and applications including MOSFET scaling, short channel effects, narrow channel effects, physical limits of small device geometry, and device packaging. It covers the following key points: 1. MOSFET scaling aims to reduce device dimensions for high density chips but is limited by physical effects. Constant field and constant voltage scaling approaches are described. 2. Short channel effects like threshold voltage reduction and mobility reduction occur as devices shrink. Narrow channel effects also impact device characteristics. 3. Packaging is important for connecting chips to external circuits, dissipating heat, and protecting the die from environmental factors. Different packaging types and their characteristics are outlined.

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skh_1987
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147 views

Unit2 - MOS Scaling and Packaging

This document discusses VLSI technology and applications including MOSFET scaling, short channel effects, narrow channel effects, physical limits of small device geometry, and device packaging. It covers the following key points: 1. MOSFET scaling aims to reduce device dimensions for high density chips but is limited by physical effects. Constant field and constant voltage scaling approaches are described. 2. Short channel effects like threshold voltage reduction and mobility reduction occur as devices shrink. Narrow channel effects also impact device characteristics. 3. Packaging is important for connecting chips to external circuits, dissipating heat, and protecting the die from environmental factors. Different packaging types and their characteristics are outlined.

Uploaded by

skh_1987
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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VLSI Technology and Applications

MOSFET Scaling
Constant Field Scaling
Constant Voltage Scaling
Short Channel Effects
Narrow Channel effects
Limits of Small Device geometry
Device Packaging

MOSFET Scaling
For high density chips: Size of MOSFET as small as possible.
Scaling: Reduction in device dimensions (operational
characteristics will be same).
Physical limits restrict the extent of scaling.
Scaling Factor, S>1

Types of Scaling
1. Constant Field Scaling
2. Constant Voltage Scaling

1. Constant Field Scaling: Attempt to preserve the magnitude


of internal electric field.
Scale all potential proportionally
Scaling: L, W, Tox, xj, Vds, Vgs all divide by S
Doping: NA, ND multiplied by S
Significant reduction in power dissipation: P/S2
Cg: Scaled by S; Charging and Discharging improved
Reduction in various parasitic capacitance
CFS: not practical in some applications:
eg. Peripheral and interface circuitry may require certain voltage level
for all I/P & O/P devices.

1. Constant Voltage Scaling: All dimensions reduces by factor


S, but terminal voltages kept constant.
Doing density increased by S2 in order to preserve charge field
relations.
Scaling: L, W, Tox, xj, all divide by S
Terminal voltages constant: Vds, Vgs (Remain same)
Doping: NA, ND multiplied by S2
As voltage constant, power dissipation increased

Short Channel Effects


Mobility reduction
Vth reduction

Vth Reduction

Short Channel Effects

DIBL: As Vds increases, current starts flowing from S to


D without applying Vgs.
Sub threshold Leakage Current: Due to Vth reduction

Narrow Channel Effects


W of the order of xdm
I-V characteristics diff. from GCA
Cause of discrepancy: reduction in Tox and Fringe charge

Hot Electron Effect


At high Vds, at which lateral electric field accelerate the channel carriers

Physical Limits and Effects


Tox Reduction: Due to physical limit.
Difficult to process a very thin layer.
Break down field effect
Punch Through: For larger Vds, depletion region of D can
extend farther toward S and the two depletion regions
can eventually merge.
Id in crease sharply
Device damage permanently

11

Chip Packaging

12

Packaging

Bringing signals & supply wires I/O of silicon die.

Remove heat generated by circuit.

Provide mechanical support.

Protect die against environmental conditions such as moisture.

13

Need of Packaging

Many high performance VLSI chips fail after packaging.


Length of wire b/w the chip and package determine the
inductive voltage drop in the o/p circuit.
A good package should provide low thermal resistance.
Choice of proper packaging technology is critical to the success
of chip development.

Important Packaging Concerns are:


Prevent the penetration of moisture.
Thermal conductivity & thermal expansion coefficient.
Pin density
Parasitic inductances and capacitances.
-partials protection.
14

Packaging Important Factors


Electrical: Low Parasitic capacitance, inductance
and resistance.
Mechanical: Reliable and robust
Thermal: Efficient heat removal
Economical: Cheap
Cost of heat sink, liquid cooling hardware, heat pipes and fan.

15

Packaging PINs Count

Increasing complexity of IC on single die also translates into a


need for more I/O pins.

Pin Count: By E. Rent


Rents Rule: P = K x GB
P=no. of pins
K=average no. of I/O per gate
G=no. of gates
B=Rent exponent (0.1 to 0.7)
Value of B depends on application area, architecture and
organization of the circuit

16

Packaging Classifications
According to soldering methods
According to material used

17

Packaging Classifications
According to soldering methods
1. Trough Hole Mounting: Require precise hole be drilled in PCB, which
is not cost effective. Inexpensive soldering process.
2. Surface Mount: The package pins can be directly soldered on the
PCB. SMT more cost & space effective. More expensive soldering
equipment required.

18

(a) Through-Hole Mounting

(b) Surface Mount

Packaging Classifications
According to material used
1. Plastic packaging: Dominating material for IC
packaging. Low cost but permeable to environmental
moisture. Heat dissipate 1 w to 2 w. Chip dissipating over
20 w requires special heat sink attachments.

2. Ceramic Packaging: High performance, power


dissipation, relatively high cost.

19

IC Packaging Types

20

Dual-In-Line package (DIP)


Pin Grid Array (PGA) package
Chip Carrier package (CCP)
Multiple chip module

IC Packaging Types
Dual-In-Line package (DIP): Through Hole Mounting
(Periphery pins).

Adv.: Low cost


Disadv.:
High interconnect inductance, which leads to significant noise
problem in high frequency application.
Maximum pin count limited to 64.

21

IC Packaging Types
Pin Grid Array (PGA) Package: Leads on entire bottom
surface instead of only on periphery.
PGA package require large PCB area and package cost is higher
than DIP.
PGA can have large pin count (over 400 pins are possible).
Adv.: PGA has less parasitic capacitance and inductance than DIP.
Disadv.: Weaken board, because of holes on whole body.

22

IC Packaging Types
Chip Carrier package (CCP) SMT (Surface Mounted
Technology) package
Leadless chip carrier: mounted directly on PCB, high pin
count.
Leaded chip carrier:

23

Multiple-Chip Modules

Very high performance, multiple chips are assembled on a common


substrate contained a single package.
Adv.: Small system size, reduced package lead count, faster operation as
chips placed very close.

24

Interconnect Levels of packaging


Chip to Substrate
Substrate to Leads or Pins

25

Bonding Techniques

Wires must be attached serially, one after the other. This leads to
longer manufacturing times with increasing pin count.
Large pin count makes more complexity.
Inferior electrical properties such as individual inductance.

Wire Bonding

Substrate
Die
Pad

Lead Frame
26

Tape-Automated Bonding (TAB)

27

New Technique
Die is attached to a metal lead frame that is printed on a polymer film.
Adv.: Automatic process, connections made simultaneously, eliminate long
wires,

Package Types
Leadless
Chip
Carrier

DIP

Quad flat
pack

Die

Small
outline IC

PGA
Plastic
Lead Chip
Carrier
28

29

Layout Design Rules (sample set)


Rule number
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11

Description
Minimum active area width
Minimum active area spacing
Minimum poly width
Minimum poly spacing
Minimum gate extension of poly over active
Minimum poly-active edge spacing
(poly outside active area)
Minimum poly-active edge spacing
(poly inside active area)
Minimum metal width
Minimum metal spacing
Poly contact size
Minimum poly contact spacing

-Rule
3
3
2
2
2
1
3
3
3
2
2

Layout Design Rules (sample set)


Rule number
R12
R13
R14
R15
R16
R17
R18
R19
R20

Description

Minimum poly contact to poly edge spacing


Minimum poly contact to metal edge spacing
Minimum poly contact to active edge spacing
Active contact size
Minimum active contact spacing
(on the same active region)
Minimum active contact to active edge spacing
Minimum active contact to metal edge spacing
Minimum active contact to poly edge spacing
Minimum active contact spacing
(on different active regions)

-Rule
1
1
3
2
2
1
1
3
6

Layout Design Rules

Layout Design Rules

Layout Design Rules

Layout Design Rules

Layout Basics

Flow of Data Between the Design House and the Foundry

Two Types of design Rules: Resolution and Alignment

Alternative Layout of a Minimum Transistor

Alternative Layout of a Minimum Transistor

MOS Layout and Schematic for SPICE Modeling

MOSIS Layout Design Rules

Design Flow for Production


of a Mask Layout

Design Flow for Production


of a Mask Layout

Design Rules Which Determines the Dimensions of a


Minimum-Size Transistor

Design Rules Which Determinene the Separation b/w the nMOS & pMOS
transistor of the CMOS Inverter

Complete Layout of the CMOS Inverter

Simplified Design Rules


Conservative rules to get you started

Fabrication and Layout

Slide 53

Inverter Layout
Transistor dimensions specified as Width /
Length
Minimum size is 4 / 2sometimes called 1
unit
For 0.6 m process, W=1.2 m, L=0.6 m

Fabrication and Layout

Slide 54

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