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Lecture 4 8-Bit+AVR+Instruction+SetLec4

This document provides information about the 8-bit AVR instruction set including: - Details of the status register and its flags. - Explanations of registers, operands, and addressing modes used by AVR instructions. - Descriptions of various addressing modes including register direct, I/O direct, direct data, indirect with displacement, and others. - Brief explanations of common instructions such as ADD, AND, CALL, CP, DEC, INC, LD, LDI, LDS, MOV, OR, and more.

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chusmanullah
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123 views

Lecture 4 8-Bit+AVR+Instruction+SetLec4

This document provides information about the 8-bit AVR instruction set including: - Details of the status register and its flags. - Explanations of registers, operands, and addressing modes used by AVR instructions. - Descriptions of various addressing modes including register direct, I/O direct, direct data, indirect with displacement, and others. - Brief explanations of common instructions such as ADD, AND, CALL, CP, DEC, INC, LD, LDI, LDS, MOV, OR, and more.

Uploaded by

chusmanullah
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Lecture 4

8-bit AVR Instruction Set


Status Register (SREG)
 SREG: Status Register
 C: Carry Flag
 Z: Zero Flag
 N: Negative Flag
 V: Two’s complement overflow indicator
 S: N +V, For signed tests
 H: Half Carry Flag
 T: Transfer bit used by BLD and BST
instructions.
 I: Global Interrupt Enable/Disable Flag
Registers and Operands
 Rd: Destination (and source) register
 Rr: Source Register
 R: Result after instruction is executed
 K: Constant data
 K: constant address
 b: Bit in Register File or I/O Register (3-bit)
 s: Bit in the Status Register (3-bit)
 X, Y, Z: Indirect Address Register
(X=R27:R26, Y=R29:R28 and Z=R31:R30)
 A: I/O location address
 q: Displacement for direct addressing (6-bit)
The program and Data addressing modes

 RISC MC supports powerful and efficient


addressing modes for access to the
Program memory (Flash) and Data
memory (SRAM, Register file, I/O
Memory, and extended I/O Memory).
 In the following figures, OP means the
operation code part of the instruction word.
Register Direct, Single Register Rd

E.g. Inc Rd
Register Direct, Two Registers Rd and Rr

Operands are contained in register r (Rr) and d(Rd).


The result is stored in register d (Rd).
E.G ADD Rd, Rs
I/O Direct Addressing

 Operand address is contained in 6 bits of the instruction word. N is the destination or


source register address.
 E.g In Rd, PORTADDRESS ; Out PORTADDRESS,Rs
Direct Data Addressing

 A 16-bit Data Address is contained in the 16 LSBs of a two-


word instruction. Rd/Rr specify the destination or source
register. E.g. LDS Rd, K;K is a 16-bit address. STS K, Rs.
Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents


Data Indirect Addressing

Operand address is the result of the X-, Y- or Z-register.


E.g. LD Rd, X. (X is the Pointer Register)
LD Rd, X+. X is pointer and is incremented after load.
Data Indirect with Pre-decrement

 The X-, Y-, or the Z-register is decremented before the


operation. Operand address is the decremented
contents of the X-, Y-, or the Z-register.
Data Indirect with Post-increment

 The X-, Y-, or the Z-register is incremented after


the operation. Operand address is the content of
the X-, Y-, or the Z-register prior to incrementing
Direct Program Addressing, JMP and
CALL

 Program execution continues at the


address immediate in the instruction word.
Indirect Program Addressing, IJMP and
ICALL

 Program execution continues at address


contained by the Z-register (i.e., the PC is
loaded with the contents of the Z-register
Relative Program Addressing, RJMP and
RCALL

 Program execution continues at address


PC+k+1. The relative address k is from -2048 to
2047.
ADD – Add without Carry
ADD – Add without Carry
ADD – Add without carry
AND – Logical AND
AND – Logical AND
AND – Logical AND
BREQ – Branch if Equal
BRGE – Branch if Greater or Equal
(Signed)
BRLO – Branch if Lower (Unsigned)
BRNE – Branch if not Equal
CALL – Long call to a subroutine
CBR – Clear Bits in Register
CLR – Clear Register
COM – One’s Complement
CP - Compare
DEC - Decrement
IN – Load an I/O Location to Register
INC - Increment
LD – Load Indirect from Data Space to
Register using Index X
LDI – Load Immediate
LDS(16-bit) – Load Direct from Data
Space
LSL – Logical Shift Left
LSR – Logical Shift Right
MOV – Copy Register
MUL – Multiply Unsigned
NEG – Two’s Complement
OR – Logical OR
OUT – Store Register to I/O Location
POP – Pop Register from Stack
PUSH – Push Register on Stack
SBIS – Skip if Bit in I/O Register is Set
SBIC – Skip if Bit in I/O Register is
Cleared
ST – Store Indirect from Register to Data
Space using Index X
STS – Store Direct to Data Space
SWAP – Swap Nibbles

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