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Power HEMT Fabrication Process

This document outlines the fabrication process for a power HEMT using a field plate. It describes 5 different transistor structures that will be fabricated including: 1) a basic HEMT without a field plate, 2) a HEMT with a gate field plate, 3) a HEMT with a separated field plate, 4) a HEMT with a dual sloped field plate, and 5) a HEMT with a slanted field plate. The fabrication process involves 5 photolithography steps and etching of silicon nitride and GaN to define contacts and isolate devices. Parameters like field plate length and distance from the drain are varied. References are provided on previous work on field plate HEMT design and fabrication.

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Vivek Surana
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180 views

Power HEMT Fabrication Process

This document outlines the fabrication process for a power HEMT using a field plate. It describes 5 different transistor structures that will be fabricated including: 1) a basic HEMT without a field plate, 2) a HEMT with a gate field plate, 3) a HEMT with a separated field plate, 4) a HEMT with a dual sloped field plate, and 5) a HEMT with a slanted field plate. The fabrication process involves 5 photolithography steps and etching of silicon nitride and GaN to define contacts and isolate devices. Parameters like field plate length and distance from the drain are varied. References are provided on previous work on field plate HEMT design and fabrication.

Uploaded by

Vivek Surana
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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Fabrication plan for

Power HEMT using field


plate
Submitted By :- Vivek Kumar Surana

Structure to be used

12 nm Al0.30Ga0.70N
10 nm
Al2
Ga0.70
N:Si
nm
Al0.30
Ga0.70N
0.30
1 nm AlN

140nm GaN
0.42m Al0.10Ga0.90N
70 nm Grad up to
Al0.10
Ganm
70
AlN (HT)
0.90N

3 SiC

STEP 1
SiNx passivation 300nm
SiNx

Technical parameters
Deosited by ICPCVD
SiH4/N2/Ar=2.8/9/90sccm
Power 200W
Pressure 35mTorr
Substrate Temp 3500C
*measured Refractive index 2.0[1]

Step 2 First step lithography ,Si3N4


etching and Mesa formation
200um

400um

Si3N4

GaN

Step 2 ICPRIE to remove 2 DEG and Isolate the transistor

Process Details
SiNx Contact opening is by
CF4/O2(40/5 sccm)based ICPRIE RF power 20 W
Pressure 10mTorr
And then GaN/AlGaN surface etch by 11nm by Cl2/BCl3
based ICPRIE

Process details
Cl2/BCl3
Gas flow(Cl2/BCl3/Ar)=10/10/5 sccm
RF power 15w
Pressure 5mTorr
Etch rate 38 nm/min
After mesa isolation clean wafer in Solvent and Dipped
in HF:NH4F(1:7) for 1min(prior to SiNX deposition)[1]

Step 2 2nd level Litho and etching of


SiNx for Source Drain contact
formation

Step 3 Source drain Contact


Formation
Standard Ohmic contact formation(Ti/Al/Ni/Au)
RTP 8300C

Step 4 3rd level litho


Gate foot Definition
Gate Contact Formation Ni/Au contact
Source

Gate

Drain

Parameter of Devices
Lsg= 1m
Lgd= 4m
Lg=5m(For DSA devices)
Lg=1m(EBL Devices)[2]

Structure 1
Step 1 to 4 to construct HEMT without field plate

Structure 2 Only Gate Field plate


Step 1 to 5
Extension of Gate metal to SiNx with 4th level litho
Si3N4
Field plate
drain

Structure 2
Same mask with FP length of .4,.8,1.2,1.6m
LFD=3.6,3.2,2.8,2.4 m[2,3]

Some Extra Structures

Structure 3 Field plate formation(Not


in direct contact with gate)
Parameter same as last Device
Advantage of using Different
metal than Gate contact(Ti/Au has
been reported).

Structure 4 Dual field plate


Sloped gate more effectively
supress the electric field .
It enables the bottom Ni contact
layer to completely cover the
gate sidewall preventing Au
diffusion
Sloped gate is made by
increasing pressure during
ICPRIE(100mTorr in this case)
A post annealing process was
carried out at 400 C for 5 min in

Fabrication parameters
LFP= 1,2,3 m[1]
LFPD=1,2,3m
Need a different mask for first lithography.

Structure 5

Procedure to form Slanted field plate


SiNx is etched at high pressure.[4]
Gate metal is deposited by e beam evaporation.
Sample is put at 150 to incident metal flux and rotated
to form a slanted field plate

Effect of Field Plate Shape

Fig 8Simulated equipotential contour lines in AlGaN/GaN HEMTs for (a)


without FP, (b) single FP, (c) multistep FP, and (d) graded FP. The applied
drain voltage is 100 V[4].

Process plan
Structure 1 and 2 can be fabricated with a single mask
Structure 4 Require different mask(dedicated to that
transistor) for both level
Structure 5 can be done by same mask as Structure 2.

Reference
(1) State-of-the-Art AlGaNGaN-on-Si Heterojunction Field
Effect Transistors with Dual Field plate_IOP_2012
http://mdcl.snu.ac.kr/pub_jour_inter/2012/I_journal_84.pdf
(2) 10 Wmm AlGaNGaN HFET with a field modulating
plate_IEEE_2002
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnum
ber=1210824
(3) Influence of the SourceGate Distance on the
AlGaNGaN HEMT Performance_IEEE_2007
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnum
ber=4160137

Reference
(4) High Breakdown Voltage Achieved on AlGaN/GaN
HEMTs With Integrated Slant Field Plates_IEEE_2006
http://ieeexplore.ieee.org/xpl/abstractAuthors.jsp?ar
number=1683855
(5) Low-loss and high-voltage III-nitride transistors for
power switching applications_IEEE_2015
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnum
ber=6967816

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