TIMERS and COUNTERS

Many applications need to

Count an Event
Generate Time Delays
The AVR MEGA 2560 has 6 Timer/Counter registers (counter register) of 8-bit and 16-bit.
They are:
8-bit

16-bit

1. Timer/Counter 2. Timer/Counter
0
1
3. Timer/Counter 4. Timer/Counter
2
3
5. Timer/Counter
4

Counter:
Basic steps for Counter Register in counting an event:
Connect External Event Source to the associated Clock Pin of counter register
When event occurs externally, the contents of counter register is incremented

Timers:
Basic steps for Counter Register in generating time delays:
Connect the Oscillator (Internal Oscillator) to the Clock Pin of the Counter
When the oscillator ticks, the content of the counter register is incremented
the content of the counter register represents, how many ticks have occurred
Since Crystal Frequency is known, calculate the tick period.
Multiply tick period with the content of the counter register
Mode of Operation-1 (Normal Mode)
Mode of Operation-2 (CTC Mode)
Load the counter register
Clear the counter register
Wait until the counter register overflows
Wait until the counter reaches a number
And the flag is SET
And the flag is SET
Example:
Example:
Consider Oscillator Frequency = 1 MHz with 8-bit register.
Then, content of counter register increment 1/1MHz = 1s.
So, if we want a time delay of 3s:
Load the counter register with 0xFD
Wait until flag is set after 3 ticks b/c of overflow
Flag should be cleared by the software (programmer)
With First Tick, content of register increment to 0xFE, Second
Tick: 0xFF, Third Tick: Overflow (0x00) and flag is SET

Consider Oscillator Frequency = 1 MHz

Then, content of counter register increment 1/1MHz = 1s.
So, if we want a time delay of 100s:
Clear the counter
Wait until it becomes equal to 100
Flag is set when counter register overflows
Flag should be cleared by the software (programmer)

Programming of Timers:
Every timer needs a Clock Pulse to Tick. Clock Source can be internal or External.
Internal Clock Source
= Timers
External Clock Source on AVR pins = Counter

Timer/Counter0 (8-bit) and Timer/Counter1 (16-bit)

[Do by yourself]
Timer/Counter2, Timer/Counter3, Timer/Counter4, Timer/Counter5

8-bit Timer/Counter0
8-bit Registers
TCCRnx, TCNTn,
OCRnx, TIFRn,
TIMSKn

Write a program to toggle all the bits of PORTK continuously with some delay. Use Timer0,
Normal mode, and no prescaler option to generate delay.
#include <avr/io.h>
void fordelay()
{
TCNT0 = 0x20;
// load TCNT0
TCCR0A = 0x00;
// Timer0
TCCR0B = 0x01;
// Normal Mode, No prescaler
while((TIFR0 & 0x1) == 0); // wait for TOV0 to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = 0x1;
// clear TOV0
}
int main (void)
{
DDRK = 0xFF;
// OUTPUT
while(1)
{
PORTK = 0xFF;
fordelay();
PORTK = 0x00;
fordelay();
}
return
0;
}

TCCR0A Timer/Counter Control Register A

Bits 7:6 COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. When OC0A is connected to the pin, the function of the
COM0A1:0 bits depends on the WGM02:0 bit setting.

Bits 5:4 COM0B1:0: Compare Match Output B Mode

These bits control the Output Compare pin (OC0B) behavior. When OC0B is connected to the pin, the function of the
COM0B1:0 bits depends on the WGM02:0 bit setting.

Bits 3, 2 Res: Reserved Bits

These bits are reserved bits and will always read as zero.

 Bits 1:0 WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting sequence of the counter, the source
for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes.

TCCR0B Timer/Counter Control Register B

Bit 7 FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
Bit 6 FOC0B: Force Output Compare B
The FOC0B bit is only active when the WGM bits specify a non-PWM mode.
Bits 5:4 Res: Reserved Bits
These bits are reserved bits and will always read as zero.
Bit 3 WGM02: Waveform Generation Mode
(already explained in slide-6)
Bits 2:0 CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter

TCNT0 Timer/Counter Register

The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing
to the TCNT0 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT0) while
the counter is running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

OCR0A Output Compare Register A

The Output Compare Register A contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match
can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0A pin.

OCR0B Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match
can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC0B pin.

TIFR0 Timer/Counter 0 Interrupt Flag Register

Bits 7:3, 0 Res: Reserved Bits

These bits are reserved bits and will always read as zero.
Bit 2 OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in OCR0B Output Compare
Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
Bit 1 OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A Output Compare
Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is
cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
Bit 0 TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit,
TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
The setting of this flag is dependent of the WGM02:0 bit setting.

TIMSK0 Timer/Counter Interrupt Mask Register

Bits 7:3, 0 Res: Reserved Bits

These bits are reserved bits and will always read as zero.
Bit 2 OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is
enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter occurs, that is, when the OCF0B bit is set in
the Timer/Counter Interrupt Flag Register TIFR0.
Bit 1 OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Compare Match A interrupt is
enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter0 occurs, that is, when the OCF0A bit is set
in the Timer/Counter 0 Interrupt Flag Register TIFR0.
Bit 0 TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter0 Overflow interrupt is enabled.
The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the
Timer/Counter 0 Interrupt Flag Register TIFR0.

Steps to Program Timer/Counter0 in Normal Mode:

1. Load the TCNT0 register with the initial value.
2. Load the values into the TCCR0A and TCCR0B registers. When you select the clock source,
the timer/counter starts to count (during sequential execution of code), and each tick causes the
content of the timer/counter to increment by 1.
3. Keep monitoring the timer overflow flag (TOV0) to see if it is set. Get out of the loop when
TOV0 raised.
4. Stop the timer by disconnecting the clock source (TCCR0B=0x00).
5. Clear the TOV0 flag for the next round.
6. Go back to step 1 to load TCNT0 again.
Calculating Delay Length Using Timers
a) Crystal Frequency
b) Prescalor factor
c) C complier,b/c various C compliers generate different hex code sizes, and the amount of
overhead due to instructions varies by complier (verify using an Oscilloscope).

Calculate the amount of delay generated by the timer. Assume crystal frequency 16MHz.
Counter Delay = Number of Counts (Ticks) * Period of each Clock
void fordelay()
{
TCNT0 = 0xF2;
// load TCNT0
TCCR0A = 0x00;
// Timer0, Normal Mode
TCCR0B = 0x01;
// No prescaler
while((TIFR0 & 0x1) == 0); // wait for TOV0 to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = 0x1;
// clear TOV0
}

number of counts (Ticks) = 0xFF 0xF2 = 0x0D (13 decimal)

Add 1 to 13 because of extra clock needed when it roll over from FF to 00 and raises the TOV0 flag.
number of counts (Ticks) = 0xFF 0xF2 = 0x0D (13 decimal) + 1 = 0x0E (14)
F = 16MHz
Counter Delay = ( 0xFF XX (ticks) + 1 ) *
Each clock has a period of T = 1 / 16MHz = 62.5ns
T
Counter delay is = number of counts (Ticks) * Period of each Clock
Counter delay is = 14 * 62.5ns = 875ns

Write a program to toggle all the bits of PORTK continuously with some delay. Use Timer0,
Normal mode, and no prescaler option to generate delay.
#include <avr/io.h>
void fordelay()
{
TCNT0 = 0x20;
// load TCNT0
TCCR0A = 0x00;
// Timer0, Normal Mode
TCCR0B = 0x01;
// No prescaler
while((TIFR0 & 0x1) == 0); // wait for TOV0 to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = 0x1;
// clear TOV0
}
int main (void)
{
DDRK = 0xFF;
// OUTPUT
while(1)
{
PORTK = 0xFF;
fordelay();
PORTK = 0x00;
fordelay();
}
return
0;
}

F = 16MHz
T = 1/16MHz = 62.5ns
Value (Ticks) = ( 0xFF - XX + 1 )
Delay = ( 0xFF - XX + 1 ) * 62.5ns
Value = 0xFF 0x20 + 1 = 0xE0 (224)
Delay = 224 * 62.5ns = 14s

Find the value to load into the timer:

Assume that we know the amount of timer delay and to find the value to load in register TCNT0.
Here are the following steps:
1. Calculate Period = T = 1 / F (with no prescaler)
[For prescaler mode = F / prescaler value, T = 1 / F]
2. Clocks = Desired Time Delay / T
3. Convert this value into hex
4. Value = 0xFF Clocks + 1
5. Set TCNT0 = Value

Write a program to toggle bit 4 of PORTK continuously every 70s. Use Timer0, Normal mode,
and 1:8 prescaler to generate the delay. Assume XTAL = 16MHz.
F = 16MHz
F/F(Prescaler) = 16MHz / 8 = 2MHz
T = 1/2MHz = 500ns
Clocks = Required Time / T
Clocks = 70s / 500ns = 140 => 0x8C
Value = 0xFF 0x8C + 1 = 0x74

#include <avr/io.h>
void fordelay()
{
TCNT0 = 0x74;
// load TCNT0
TCCR0A = 0x00;
// Timer0, Normal Mode
TCCR0B = 0x02;
// No prescaler
while((TIFR0 & (1<<TOV0)) == 0); // wait for TOV0 to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = 0x1<<TOV0;
// clear TOV0
}
int main (void)
{
DDRK = 0xFF;
// OUTPUT
while(1)
{
PORTK |= (1<<4);
fordelay();
PORTK &= ~(1<<4);
fordelay();
}
return
0;
}

Assume XTAL = 16MHz. Write a program to generate a square wave of 64KHz on bit 3 of
PORTK continuously.
Look at the following steps:
1.
2.
3.
4.
5.

Frequency Required = 64KHz

T Required = 1/64KHz = 15.625s the period of square wave
1 / 2 of it for the high and low portion of pulse is 7.8125s
Clocks = Required Time / T = 7.8125s / 62.5ns = 125 => 0x7D
Value = 0xFF 0x7D + 1 = 0x83

Generate Maximum Time Delay and Minimum Time Delay. Assume XTAL = 16MHz.
Assume XTAL = 16MHz. Write a program to generate a square wave of 16KHz on bit 3 of
PORTK continuously.
(Hint : Use Prescaler)
Write a program to generate a square wave of 125Hz on bit 3 of PORTK continuously

Clear Timer on Compare (CRC) Match Mode Programming:

As with Normal Mode, CRC Mode timer is incremented with a clock. But it counts up until the
content of the TCNT0 register becomes equal to the content of OCR0A, then timer will be cleared.
OCF0A flag will be set when the next clock occur. OCF0A flag is located in the TIFR0 register.
Initialize OCF0A with 0x09
void fordelay()
{
TCNT0 = 0x00;
// load TCNT0
OCR0A = 0x09;
// load OCR0A
TCCR0A = 0x01;
// Timer0, CRC Mode
TCCR0B = 0x01;
// No prescaler
while((TIFR0 & 0x2) == 0); // wait for OCF0A to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = 0x2;
// clear OCF0A
}

Assume XTAL = 16MHz. Write a program to generate a delay of 1ms to toggle bit 4 of PORTK
continuously. Use Timer0, CTC mode, and with prescaler = 64.
T = 64 * 62.5ns = 4s
Clocks = 1ms / 4s = 250
Value = 250 1 = 249 (0xF9)
void fordelay()
{
TCNT0 = 0x00;
// load TCNT0
OCR0A = 0xF9;
// load OCR0A
TCCR0A = 0x01;
// Timer0, CRC Mode
TCCR0B = 0x01;
// No prescaler
while((TIFR0 & (1<<OCF0A)) == 0);//wait for OCF0A to roll over
TCCR0B = 0x00;
// stop the clock source
TIFR0 = (1<< OCF0A);
// clear OCF0A
}
Write a program to generate a delay of 750s

Write a program to generate a delay of 750s.

If TCNT0 = 95 and OCR0A = 89. Find the delay when bit 3 of PORTK get high, and also find,
for how much time it stay high.

16-bit Timer/Counter1
16-bit Registers
TCNTn, OCRnx
ICRn(to calculate frequency, duty-cycle, etc.)
8-bit Registers
TCCRnx, TIFRn, TIMSKn
(n = 0-5, x = A or B)

TCCR1A Timer/Counter 1 Control Register A

Bit 7:6 COMnA1:0: Compare Output Mode for Channel A

Bit 5:4 COMnB1:0: Compare Output Mode for Channel B
Bit 3:2 COMnC1:0: Compare Output Mode for Channel C
The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior.
If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is
connected to (Same for OCnB, and OCnC).

Bit 1:0 WGMn1:0: Waveform Generation Mode

Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes.

TCCR1B Timer/Counter 1 Control Register B

Bit 7 ICNCn: Input Capture Noise Canceler

Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the
Input Capture Pin (ICPn) is filtered. The filter function requires four successive equal valued samples of the ICPn pin for changing
its output. The input capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture event. When the ICESn bit is written to
zero, a falling (negative) edge is used as trigger, and when the ICESn bit is written to one, rising (positive) edge will trigger capture.
Bit 5 Reserved Bit
This bit is reserved for future use. This bit must be written to zero when TCCRnB is written.
Bit 4:3 WGMn3:2: Waveform Generation Mode
See TCCRnA Register.
Bit 2:0 CSn2:0: Clock Select
The three clock select bits select
the clock source to be used by
the Timer/Counter.

TCCR1C Timer/Counter 1 Control Register C

Bit 7 FOCnA: Force Output Compare for Channel A

Bit 6 FOCnB: Force Output Compare for Channel B
Bit 5 FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writing a logical one
to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the waveform generation unit.
The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting.
Bit 4:0 Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to
zero when TCCRnC is written.

TCNT1H and TCNT1L Timer/Counter 1

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read and for write
operations, to the Timer/Counter unit 16-bit counter.

OCR1AH and OCR1AL Output Compare Register 1 A

OCR1BH and OCR1BL Output Compare Register 1 B

OCR1CH and OCR1CL Output Compare Register 1 C

The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNTn).

ICR1H and ICR1L Input Capture Register 1

The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the ICPn pin.

TIFR1 Timer/Counter1 Interrupt Flag Register

Bit 5 ICFn: Timer/Countern, Input Capture Flag

This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register (ICRn) is set by the WGMn3:0 to be
used as the TOP value, the ICFn Flag is set when the counter reaches the TOP value.
Bit 3 OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register C (OCRnC).
Bit 2 OCFnB: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output Compare Register B (OCRnB).
Bit 1 OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn value matches the Output Compare Register A (OCRnA).
Bit 0 TOVn: Timer/Countern, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes, the TOVn Flag is set
when the timer overflows.

TIMSK1 Timer/Counter 1 Interrupt Mask Register

Bit 5 ICIEn: Timer/Countern, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input
Capture interrupt is enabled. The corresponding Interrupt Vector is executed when the ICFn Flag, located in TIFRn, is set.
Bit 3 OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output
Compare C Match interrupt is enabled. The corresponding Interrupt Vector is executed when the OCFnC Flag, located in TIFRn, is s
Bit 2 OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see Interrupts on page 101) is executed when the OCFnB Flag, located in TIFRn, is set.
Bit 1 OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see Interrupts on page 101) is executed when the OCFnA Flag, located in TIFRn, is set.
Bit 0 TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (see Interrupts on page 101) is
executed when the TOVn Flag, located in TIFRn, is set.

Assume XTAL = 16MHz. Write a program to generate a delay of 25.6ms to toggle bit 4 of PORTK
continuously. Use Timer1, Normal mode, and with prescaler = ???
#include <avr/io.h>
void fordelay()
{
TCNT1H = 0xC8;
TCNT1L = 0x00;
TCCR1A = 0x00;
// load TCNT0
TCCR1B = 0x02;
// Timer0, Normal Mode
TCCR1C = 0x00;
// No prescaler
while((TIFR1 & 0x1) == 0);
// wait for TOV0 to roll over
TCCR1B = 0x00;
// stop the clock source
TIFR1 = 0x1;
// clear TOV0
}
int main (void)
{
DDRK = 0xFF; // OUTPUT
while(1)
{
PORTK = 0xFF;
fordelay();
PORTK = 0x00;
fordelay();
}
return
0;
}

Prescaler
No
Prescaler
(1/8)
(1/64)
(1/256)
(1/1024)

Frequenc Time
y
Period
16MHz 6.25E-08
0.000000
5
250000 0.000004
62500 0.000016
15625 0.000064

2000000

Clocks

Value
(hex)

40960
64000
0
51200

C800

6400
1600
400

1900
640
190

Assume XTAL = 16MHz. Write a program to generate a delay of 1s to toggle bit 4 of PORTK
continuously. Use Timer1, Normal mode, and with prescaler = ???
#include <avr/io.h>
void fordelay()
{
TCNT1H = 0xF4;
TCNT1L = 0x24;
TCCR1A = 0x00;
// load TCNT0
TCCR1B = 0x04;
// Timer0, Normal Mode
TCCR1C = 0x00;
// No prescaler
while((TIFR1 & 0x1) == 0);
// wait for TOV0 to roll over
TCCR1B = 0x00;
// stop the clock source
TIFR1 = 0x1;
// clear TOV0
}
int main (void)
{
DDRK = 0xFF; // OUTPUT
while(1)
{
PORTK |= (1<<4);
fordelay();
PORTK &= ~(1<<4);
fordelay();
}
return
0;
}

Prescaler

Frequenc
y

Time
Period

No
Prescaler

16MHz

6.25E-08

(1/8)

2000000

(1/64)

Clocks

Value
(hex)

16000
F42400
000

0.000000 20000
1E8480
5
00

250000 0.000004

25000
0

3D090

(1/256)

62500

0.000016 62500

F424

(1/1024)

15625

0.000064 15625

3D09

Counters
AVR timer can also be used to count, detect, and measure the time of events happening outside
the AVR. When used as counter, it is a pulse outside the AVR that increments the TCNTn register.
CS bits (Clock Selector) in TCCR0B register decide the source of the clock for the timer/counter0.
If CS02:00 is set as 6 or 7, the timer is used as counter and gets pulses from a source outside the
AVR chip. For timer/counter1, CS bits (Clock Selector) in TCCR1B register decide the source of
the clock. If CS12:10 is set as 6 or 7, the timer is used as counter and gets pulses from a source
outside the AVR chip. For timer/counter0 external clock input pin is T0 (PD7/pin-50),and
for timer/counter1external clock input is T1 (PD6/pin-49).
Timer/Counter0 (As counter):
Find the value for TCCR0A and TCCR0B if we want to program Timer/Counter0 as Normal mode
counter. Use external clock for the clock source and increment on the positive edge.
TCCR0A = 0x00 and

TCCR0B = 0x07 Normal, external clock source, no prescaler

Assume that a button input is fed into pin T0, and display the counter on PORTK.
#include<avr/io.h>
int main (void)
{
PORTD = 0x80; //activate pull-up of
DDRK = 0xFF;
TCCR0A = 0x00;
TCCR0B = 0x07;
while(1)
{
do
{
PORTK = TCNT0;
}while((TIFR0 & (0x1 << TOV0)) == 0); //wait for TOV0 to roll over
TIFR0 = 0x1 << TOV0;
}
return 0;
}

Assume that a 1Hz clock pulse is fed into pin T0, use the TOV0 flag to extend Timer/Counter0 to
a 16-bit counter and display the counter on PORTF and PORTK.
#include<avr/io.h>
int main (void)
{
PORTD = 0x80; //activate pull-up of
DDRF = 0xFF;
DDRK = 0xFF;
TCCR0A = 0x00;
TCCR0B = 0x07;
while(1)
{
do
{
PORTF = TCNT0;
}while((TIFR0 & (0x1 << TOV0)) == 0); //wait for TOV0 to roll over
TIFR0 = 0x1 << TOV0;
PORTK++;
}
return 0;
}

Assume that a 50Hz clock pulse is fed into pin T5, write a program for counter5 in rising edge
mode to count the pulses and display the TCNT5H and TCNT5L registers on PORTF and PORTK.
#include<avr/io.h>
int main (void)
{
PORTL = 0x04; //activate pull-up of
DDRF = 0xFF;
DDRK = 0xFF;
TCCR5A = 0x00;
TCCR5B = 0x07;
TCCR5C = 0x00;
while(1)
{
do
{
PORTF = TCNT5L;
PORTK = TCNT5H;
}while((TIFR5 & (0x1 << TOV5)) == 0); //wait for TOV5 to roll over
TIFR5 = 0x1 << TOV5;
}
return 0;
}