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Elements of Cache Design Pentium IV Cache Organization

This document discusses cache design and organization. It begins by explaining that cache is a small, fast memory located between the CPU and main memory. When the CPU requests data from memory, the cache is checked first. If the data is present, it is retrieved from the cache. Otherwise, the block containing the data is loaded from main memory to cache. The document then discusses various cache design aspects like addressing, size, mapping functions, replacement algorithms, write policies, block size, and number of caches. It provides examples of specific cache organizations used in processors like the Pentium IV.

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52 views

Elements of Cache Design Pentium IV Cache Organization

This document discusses cache design and organization. It begins by explaining that cache is a small, fast memory located between the CPU and main memory. When the CPU requests data from memory, the cache is checked first. If the data is present, it is retrieved from the cache. Otherwise, the block containing the data is loaded from main memory to cache. The document then discusses various cache design aspects like addressing, size, mapping functions, replacement algorithms, write policies, block size, and number of caches. It provides examples of specific cache organizations used in processors like the Pentium IV.

Uploaded by

AhmadChoirul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Elements of cache

design
Pentium IV cache
organization

M. V. Wilkes, Slave Memories and Dynamic Storage Allocation,


IEEE Transactions on Electronic Computers, vol. EC-14, no. 2,
pp. 270-271, April 1965.

Small amount of fast memory


Sits between normal main memory and CPU
May be located on CPU chip

CPU requests contents of memory location


Check cache for this data
If present, get from cache (fast)
If not present, read required block from
main memory to cache
Then deliver from cache to CPU
Cache includes tags to identify which block
of main memory is in each cache slot

Addressing
Size
Mapping Function
Replacement Algorithm
Write Policy
Block Size
Number of Caches

Where does cache sit?


Between processor and virtual memory management unit
Between MMU and main memory

Logical cache (virtual cache) stores data using


virtual addresses
Processor accesses cache directly, not thorough physical
cache
Cache access faster, before MMU address translation

Physical cache stores data using main memory


physical addresses

Cost
More cache is expensive

Speed
More cache is faster (up to a point)
Checking cache for data takes time

Cache of 64kByte
Cache block of 4 bytes

i.e. cache is 16k (214) lines of 4 bytes

16MBytes main memory


24 bit address

(224=16M)

Each block of main memory maps to only


one cache line
i.e. if a block is in cache, it must be in one specific
place

Address is in two parts


Least Significant w bits identify unique word
Most Significant s bits specify one memory
block
The MSBs are split into a cache line field r
and a tag of s-r (most significant)

Tag s-r
8

Line or Slot r

Word w

14

24 bit address
2 bit word identifier (4 byte block)
22 bit block identifier
8 bit tag (=22-14)
14 bit slot or line

No two blocks in the same line have the same Tag field
Check contents of cache by finding line and checking Tag

Address length = (s + w) bits


Number of addressable units = 2s+w words
or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2s+
w/2w = 2s
Number of lines in cache = m = 2r
Size of tag = (s r) bits

Simple
Inexpensive
Fixed location for given block

If a program accesses 2 blocks that map to the


same line repeatedly, cache misses are very high

A main memory block can load into any line


of cache
Memory address is interpreted as tag and
word
Tag uniquely identifies block of memory
Every lines tag is examined for a match
Cache searching gets expensive

Tag 22 bit

Word
2 bit

22 bit tag stored with each 32 bit block of data


Compare tag field with tag entry in cache to
check for hit
Least significant 2 bits of address identify which
16 bit word is required from 32 bit data block

Address length = (s + w) bits


Number of addressable units = 2s+w words
or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2s+
w/2w = 2s
Number of lines in cache = undetermined
Size of tag = s bits

Cache is divided into a number of sets


Each set contains a number of lines
A given block maps to any line in a given
set

e.g. Block B can be in any line of set i

e.g. 2 lines per set


2 way associative mapping
A given block can be in one of 2 lines in only one
set

13 bit set number


Block number in main memory is modulo 213

Tag 9 bit

Set 13 bit

Word
2 bit

Use set field to determine cache set to look


in
Compare tag field to see if we have a hit

Address length = (s + w) bits


Number of addressable units = 2s+w words
or bytes
Block size = line size = 2w words or bytes
Number of blocks in main memory = 2d
Number of lines in set = k
Number of sets = v = 2d
Number of lines in cache = kv = k * 2d
Size of tag = (s d) bits

No choice
Each block only maps to one line
Replace that line

Hardware implemented algorithm (speed)


Least Recently used (LRU)
e.g. in 2 way set associative
First in first out (FIFO)

replace block that has been in cache longest

Least frequently used


replace block which has had fewest hits

Random

Must not overwrite a cache block unless


main memory is up to date
Multiple CPUs may have individual caches
I/O may address main memory directly

All writes go to main memory as well as


cache
Multiple CPUs can monitor main memory
traffic to keep local (to CPU) cache up to
date
Lots of traffic
Slows down writes

Remember bogus write through caches!

Updates initially made in cache only


Update bit for cache slot is set when update
occurs
If block is to be replaced, write to main
memory only if update bit is set
Other caches get out of sync
I/O must access main memory through
cache
N.B. 15% of memory references are writes

Retrieve not only desired word but a number of


adjacent words as well
Increased block size will increase hit ratio at first
the principle of locality

Hit ratio will decreases as block becomes even


bigger

Probability of using newly fetched information becomes


less than probability of reusing replaced

Larger blocks

Reduce number of blocks that fit in cache


Data overwritten shortly after being fetched
Each additional word is less local so less likely to be
needed

No definitive optimum value has been found


8 to 64 bytes seems reasonable
For HPC systems, 64- and 128-byte most common

High logic density enables caches on chip


Faster than bus access
Frees bus for other transfers

Common to use both on and off chip cache

L1 on chip, L2 off chip in static RAM


L2 access much faster than DRAM or ROM
L2 often uses separate data path
L2 may now be on chip
Resulting in L3 cache
Bus access or now on chip

80386 no on chip cache


80486 8k using 16 byte lines and four way set
associative organization
Pentium (all versions) two on chip L1 caches
Data & instructions

Pentium III L3 cache added off chip


Pentium 4
L1 caches

8k bytes
64 byte lines
four way set associative

L2 cache

Feeding both L1 caches


256k
128 byte lines
8 way set associative

L3 cache on chip

Problem

Solution

Processoronwhichfeature
firstappears

Externalmemoryslowerthanthesystembus.

Addexternalcacheusingfaster
memorytechnology.

386

Increasedprocessorspeedresultsinexternalbusbecominga
bottleneckforcacheaccess.

Moveexternalcacheonchip,
operatingatthesamespeedasthe
processor.

486

Internalcacheisrathersmall,duetolimitedspaceonchip

AddexternalL2cacheusingfaster
technologythanmainmemory

486

Createseparatedataandinstruction
caches.

Pentium

Createseparatebacksidebusthat
runsathigherspeedthanthemain
(frontside)externalbus.TheBSBis
dedicatedtotheL2cache.

PentiumPro

ContentionoccurswhenboththeInstructionPrefetcherand
theExecutionUnitsimultaneouslyrequireaccesstothe
cache.Inthatcase,thePrefetcherisstalledwhilethe
ExecutionUnitsdataaccesstakesplace.

Increasedprocessorspeedresultsinexternalbusbecominga
bottleneckforL2cacheaccess.

Someapplicationsdealwithmassivedatabasesandmust
haverapidaccesstolargeamountsofdata.Theonchip
cachesaretoosmall.

MoveL2cacheontotheprocessor
chip.

PentiumII

AddexternalL3cache.

PentiumIII

MoveL3cacheonchip.

Pentium4

Fetch/Decode Unit
Fetches instructions from L2 cache
Decode into micro-ops
Store micro-ops in L1 cache

Out of order execution logic


Schedules micro-ops
Based on data dependence and resources
May speculatively execute

Execution units
Execute micro-ops
Data from L1 cache
Results in registers

Memory subsystem
L2 cache and systems bus

Decodes instructions into RISC like micro-ops before L1 cache


Micro-ops fixed length
Superscalar pipelining and scheduling

Pentium instructions long & complex


Performance improved by separating decoding from scheduling
& pipelining
(More later ch14)

Data cache is write back


Can be configured to write through

L1 cache controlled by 2 bits in register


CD = cache disable
NW = not write through
2 instructions to invalidate (flush) cache and write back then
invalidate

L2 and L3 8-way set-associative


Line size 128 bytes

Core

Cache
Type

CacheSize(kB)

CacheLineSize
(words)

Associativity

Location

WriteBuffer
Size(words)

ARM720T

Unified

4way

Logical

ARM920T

Split

16/16D/I

64way

Logical

16

ARM926EJS

Split

4128/4128D/I

4way

Logical

16

ARM1022E

Split

16/16D/I

64way

Logical

16

ARM1026EJS

Split

4128/4128D/I

4way

Logical

IntelStrongARM

Split

16/16D/I

32way

Logical

32

IntelXscale

Split

32/32D/I

32way

Logical

32

ARM1136JFS

Split

464/464D/I

4way

Physical

32

Small FIFO write buffer

Enhances memory write performance


Between cache and main memory
Small c.f. cache
Data put in write buffer at processor clock speed
Processor continues execution
External write in parallel until empty
If buffer full, processor stalls
Data in write buffer not available until written
So keep buffer small

Manufacturer sites
Intel
ARM

Search on cache

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