Electronics - I

Digital Electronics

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NUMBER SYSTEM
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Numbers

Every number system is associated with a base or radix

A positional notation is commonly used to express numbers

(a5 a4 a3 a2 a1a0 ) r a5 r 5 a4 r 4 a3r 3 a2 r 2 a1r 1 a0 r 0

The decimal system has a base of 10 and uses symbols
(0,1,2,3,4,5,6,7,8,9) to represent numbers

(2009)10 2 103 0 10 2 0 101 9 100

(123.24)10 1102 2 101 3 100 2 10 1 4 10 2
An octal number system has a base 8 and uses symbols (0,1,2,3,4,5,6,7)

(2007)8 2 83 0 82 0 81 7 80
What decimal number does it represent?

(2007)8 2 512 0 64 0 81 7 80 1033

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A hexadecimal system has a base of 16

Number

Symbol

10

11

12

13

14

15

(2 BC 9)10 2 163 B 16 2 C 161 9 16 0

How do we convert it into decimal number?

(2 BC 9)10 2 4096 11 256 12 161 9 160 11209

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A Binary system has a base 2 and uses only two symbols

0, 1 to represent all the numbers
20

21

22

Which decimal number does this correspond to ? 23

(1101) 2 1 23 1 2 2 0 21 1 20

(1101) 2 1 8 1 4 0 21 1 20 13

1101.1001
23
2

-1

0.5

-2

0.25

-4

22

21

20

-2
2-1 2 2-3

0.125

0.0625

0.03125 0.015625

-3

-4

-5

-6

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24

16

25

32

26

64

27

128

28

256

29

512

210

1024(K)

220

1048576(M)

Developing Fluency with Binary Numbers

11001 = ?

25

1100001 = ?

64+32+1=97

0.101 = ?

0.5+0.125=0.625

11.001 = ?

3+0.125=3.125

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Converting decimal to binary number

Convert 45 to binary number

(45)10 bnbn 1.......b0

45 bn 2n bn 1 2n 1.......b1 21 b0
Divide both sides by 2

45
22.5 bn 2n 1 bn 1 2n 2.......b1 20 b0 0.5
2
22 0.5 bn 2n 1 bn 1 2n 2....... b1 20 b0 0.5

b0 1
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22 0.5 bn 2 n 1 bn 1 2n 2....... b1 20 b0 0.5

b0 1

22 bn 2n 1 bn 1 2 n 2.......b2 21 b1 20
Divide both sides by 2

22
11 bn 2n 2 bn 1 2n 3.......b2 20 b1 0.5
2

b1 0

11 bn 2n 2 bn 1 2n 3...... b3 21 b2 20
5.5 bn 2n 3 bn 1 2n 4...... b3 20 0.5b2

b2 1

5 bn 2n 3 bn 1 2n 4......b4 21 b3 20
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5 bn 2n 3 bn 1 2n 4......b4 21 b3 20
2.5 bn 2n 4 bn 1 2 n 5......b4 20 0.5b3

b3 1

2 bn 2n 4 bn 1 2 n 5......b5 21 b4 20
1 bn 2n 5 bn 1 2n 6......b5 20 0.5b4

b4 0

b5 1
(45)10 b5b4b3b2b1b0 101101

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Converting decimal to binary number

Method of successive division by 2
45

remainder

22

11

45

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101101

10

Convert (153)10 to octal number system

(153)10 (bn bn 1.......b0 )8

(153)10 bn 8n bn 18n 1.......b181 b0
Divide both sides by 8

b0
153
b0
n 1
n2
0

0.125 b0 1
19.125 bn 8 bn 18 .......b1 8
8
8
8
153

remainder

19

153

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(231)8

11

Converting decimal to binary number

Convert (0.35)10 to binary number

(0.35)10 0.b1b2b3 .......b n

0.35 0 b1 21 b2 22 .......b n 2 n
How do we find the b-1 b-2 coefficients?
Multiply both sides by 2

0.7 b1 b2 21 .......b n 2 n 1

b1 0

0.7 b2 21 b3 22 .......b n 2 n 1
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0.7 b2 21 b3 22 .......b n 2 n 1
Multiply both sides by 2

1.4 b2 b3 21 .......b n 2 n 2
Note that +1/4+1/8+1

b2 1

0.4 b3 21 b4 2 2.......b n 2 n 2
0.8 b3 b4 2 1.......b n 2 n 3

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b3 0

13

Converting decimal to binary number

0.125 = ?
0 .

0.125

(.001)2

0.

25

0.

1.

0 .

0.8125 = ?

0.8125

125

(.1101)2

x2
x2
x2

8125

1.

625

1.

25

0.

1.

x2
x2
x2
x2

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Binary numbers
Most significant bit or MSB

1011000111

decimal

2bit

3bit

4bit

5bit

00

000

0000

00000

01

001

0001

00001

10

010

0010

00010

11

011

0011

00011

100

0100

00100

101

0101

00101

110

0110

00110

111

0111

00111

1000

01000

1001

01001

10

1010

01010

11

1011

01011

Least significant
bit or LSB
This is a 10 bit number
Binary digit = bit

N-bit binary number can

represent numbers from 0 to 2N
-1

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Converting Binary to Hex and Hex to Binary

(b7b6b5b4b3b2b1b0 )b (h1 , h0 ) Hex

Number

Symb
ol

0(0000)

1(0001)

2(0010)

3(0011)

4(0100)

5(0101)

6(0110)

7(0111)

8(1000)

9(1001)

10(1010)

(110011)b (11)(0011) (33) Hex

11(1011)

12(1100)

( EC ) Hex (1110)(1100) (11101100)b

13(1101)

14(1110)

15(1111)

b7 27 b6 26 b5 25 b4 24 b3 23 b2 22 b1 21 b0 h1161 h0
(b7 23 b6 22 b5 21 b4 )24 (b3 23 b2 2 2 b1 21 b0 ) h1161 h0

h1

h0

(10110011)b (1011)(0011) ( B3) Hex

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Binary Addition/Subtraction
1

1 0

1 1

101

1101

110

+ 1110

1011

11011

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Complement of a number
9s complement
Decimal system:
10s complement
9s complement of n-digit number x is 10n -1 -x
10s complement of n-digit number x is 10n -x
9s complement of 85 ?

102 1 85

99 85 14

9's complement of 123 = 999 123 876

10's complement of 123 = 9's complement of 123+1 877
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Complement of a binary number

1s complement
Binary system:
2s complement
1s complement of n-bit number x is 2n -1 -x
2s complement of n-bit number x is 2n -x
1s complement of 1011 ?

24 1 1011

1111 1011 0100

1s complement is simply obtained by flipping a bit (changing 1 to 0 and 0 to 1)

1's complement of 1001101 = ?

0110010
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2's complement of 1010 = 1's complement of 1010+1 0110

2's complement of 110010 =
Leave all least significant 0s as they are, leave first 1 unchanged and then flip
all subsequent bits

001110
1011 0101
101101100 010010100

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Advantages of using 2s complement

x1

Adder

x2

S
CY

Can we carry out Y = X1 X2 using such an adder?

x1,x2: N bit numbers

x1

Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1

Adder
x2

2's Complement

CY

Sign
Sign = 0 for psotive numbers
= 1 for negative numbers

2 x2
N

(CY , S ) x1 2 N x2

Note that carry will be there only if x1 x2 is positive as 2N is N+1 bits (1

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Advantages of using 2s complement

x1,x2: N bit numbers

x1

Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1

Adder
x2

CY

2's Complement

Sign
Sign = 0 for psotive numbers
= 1 for negative numbers

2 N x2

(CY , S ) x1 2 N x2

Note that carry will be there only if x1 x2 is positive as 2N is N+1 bits (1

followed by N zeros)

A zero carry implies a negative number whose magnitude (x2 x1) can be found
as follows:
S x 2N x
1

2'scomplement of S 2 N ( x1 2 N x2 ) x2 x1
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Example
10

0100
S

x1=1010

0100

Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1

Adder
x2=0110

2's Complement

CY

Sign
Sign = 0 for psotive numbers
= 1 for negative numbers

1010

1010
+1010
10100

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Example
6

1100
S

x1=0110

0100

Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1

Adder
x2=1010

2's Complement

10

CY

Sign
Sign = 0 for psotive numbers
= 1 for negative numbers

0110

0110
+0110
1100
It makes sense to use adder as a subtractor as well provided additional circuit
required for carrying out 2s complement is simple
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Subtraction using 10s complement

5

x1,x2: N digit numbers

x1

5
Y = S if Sign = 0
Y = 10's Complement of S if Sign = 1

Adder
10's Complement

x2

10-3=7

CY

Sign

Sign = 0 for psotive numbers

= 1 for negative numbers

This way of subtraction would make sense only if subtracting a number x 2

from 10N is much simpler than directly subtracting it directly from x1

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Representing positive and negative binary numbers

One extra bit is required to carry sign information. Sign bit = 0
Represents positive number and Sign bit = 1 represents negative number
decimal

Signed
Magnitude

decimal

Signed 1s
complement

0000

0000

0001

0001

Signed 2s
complemen
t
0000

0010

0010

0001

0011

0011

0010

0100

0100

0011

0101

0101

0100

0110

0110

0101

0111

0111

0110

-0

1000

-0

1111

1001

1110

0111

-1

-1

1010

1101

1111

-2

-2

-1

1110

1011

1100

-2

-3

-3

1101

1100

1011

-3

-4

-4
-5

1010

-4

1100

-5

1101

-6

1001

-5

1011

-6

1110

-7

1000

-6

1010

-7

1111

-7

1001

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decimal

26

If we represent numbers in 2s complement

form carrying out subtraction is same as addition
x1,x2: N bit numbers

x1

Y = S if Sign = 0
Y = 2's Complement of S if Sign = 1

Adder
x2

CY

2's Complement

Sign
Sign = 0 for psotive numbers
= 1 for negative numbers

S
x1

Answer is in 2s
complement form

Adder
x2

CY

x1,x2: N bit numbers in 2's complement

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Example

S
x1
Adder
CY

x2

x1,x2: N bit numbers in 2's complement

+5
+2
+7

-5
+2
-3

0101
+0010
0111
1011
+0010
1101

2s complement is 0011 =

+5
-2
+3

-5
-2
-7

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0101
+1110
0011
1011
+1110
1001
28

2s complement is 0111 = 7

BOOLEAN ALGEBRA
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Boolean Algebra

Algebra on Binary numbers

A variable x can take two values {0,1}

False
0

No
Low voltage

Basic operations:

AND:

True

y = x1 . x 2

Y is 1 if and only if both x1 and x2 are 1, otherwise zero

Yes
High voltage

x1 x2 y
Truth Table

0 0 0
0 1 0
1 0 0
1 1 1
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Basic operations:

OR: y = x1 + x 2
Y is 1 if either x1 and x2 is 1. Or y= 0 if and only if both variables are zero

x1 x2 y
0
0
1
1
NOT:

y= x

0
1
0
1

0
1
1
1
x

0 1
1 0
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Boolean Algebra
Basic Postulates

P1: x + 0 = x
P2: x + y = y + x
P3: x.(y+z) = x.y+x.z

P1: x . 1 = x
P2: x . y = y . x
P3: x+y.z = (x+y).(x+z)

P4: x + x = 1

P4: x . x = 0
Basic Theorems

T1: x + x = x

T1: x . x = x

T2: x + 1 = 1

T2: x . 0 = 0

T3: ( x ) = x

T4: x . (y.z) = (x.y).z

T4: x + (y+z) = (x+y)+z

T5
T6:

(x+y) = x . y (DeMorgan's theorem)

x+ x.y = x

T5

(x.y) = x + y (DeMorgan's theorem)

T6:

x.( x+y) = x

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Proving theorems

P1: x + 0 = x
P2: x + y = y + x

P1: x . 1 = x

P3: x.(y+z) = x.y+x.z

P3: x+y.z = (x+y).(x+z)

P4: x + x = 1

P4: x . x = 0

Prove T1: x + x = x
x + x = (x+x). 1 (P1)
= (x+x). (x+x)
= x + x.x

=x+0
=x

P2: x . y = y . x

Prove T1: x . x = x
x . x = x.x+ 0 (P1)
(P4)

(P3)

= x.x + x.x

(P4)

= x . (x+x ) (P3)

(P4)

=x.1

(P1)

=x

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(P4)

(P1)

33

Proving theorems

P1: x + 0 = x
P2: x + y = y + x

P1:

x.1=x

P2:

x .y = y.x

P3: x.(y+z) = x.y+x.z

P3:

x+y.z = (x+y).(x+z)

P4: x + x = 1

P4:

x. x =0

Prove : x + 1 = 1

x + 1 = x+(x+ x)
= (x+x)+ x

=x+x

x + x .y = x
= x . 1 + x. y
= x. (1+ y)
=x.1
=x

x + x .y = x+y
= (x + x ). (x+ y)
= 1. (x+ y)
=x+y

=1
DeMorgans theorem

(x1 x 2 x 3 ....) x1 . x 2 .x 3 .
(x1. x 2 . x 3 .....) ( x1 + x 2 x 3 +.....)
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Simplification of Boolean expressions

(x1 x 2 x 3 ....) x1 . x 2 .x 3 .
(x1.x 2 x 2 .x 3 ) ?

(x1. x 2 . x 3 .....) ( x1 + x 2 x 3 +.....)

(x1 x 2 ) . (x 2 + x 3 )
x1 . x 2 x1 . x 3 x 2 . x 3

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Function of Boolean variables

x1
y
x2

x1 x2 y

y = x2

0
0
1
1

0
1
0
1

0
1
0
0

Y = 1 when x1 is 0 and x2 is 1

y = x1 . x2
Boolean expression

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Obtaining Boolean expressions from truth Table

x1 x2 y
0
0
1
1

0
1
0
1

x1 x2 y

y = x1 . x2

1
0
0
0

x1 x2 y
0
0
1
1

0
1
0
1

1
0
0
1

0
0
1
1

0
1
0
1

0
0
1
0

y = x1 . x2

x1 . x2
y = x1 . x2 x1. x2

x1 . x2
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Obtaining Boolean expressions from truth Table

x1 x2 y
0
0
1
1

0
1
0
1

0
1
1
0

y = x1 . x2 x1. x2

Instead of writing expressions as sum of terms that make y equal to 1, we

can also write expressions using terms that make y equal to 0

x1 x2 y
0
0
1
1

0
1
0
1

1
1
1
0

y = x1 . x2 x1 . x2 x1. x2

y = x1 x2
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x1 x2 y

x1 x2 y

0
0
1
1

0
0
1
1

0
1
0
1

1
0
1
1

y =x1 x2

x1 x2 y
0
0
1
1

0
1
0
1

0
1
1
0

0
1
0
1

0
1
1
1

y =x1 x2

x1 x2
y = (x1 x2 ).( x1 x2 )
x1 x2

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Obtaining Boolean expressions from truth Table

x1 x2 x3 y
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3

Sum of Products (SOP) form

y = ( x1 x2 x3 ).( x1 x2 x3 ).( x1 x2 x3 ).( x1 x2 x3 )

Product of Sum (POS) form
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IMPLEMENTATION OF
BOOLEAN EXPRESSIONS
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Elementary Gates

AND:

Implementing Boolean expressions

y = x1 . x 2

x1

AND

x2

Why call it a gate?

x1

x1

y=0

AND

Gate is closed

OR:

y = x1 + x 2

NOT:

y= x

AND

y = x1
Gate is open

x1
x2

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OR

y
42

x1

NAND: y = x1. x 2

x2

x1
x2

NOR: y = x1 + x 2

x1x2

NAND

x1
x2

x1
x2

x1x2

AND

x1+x2
x1+x2

OR

NOR

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x1 x2 y

y = x1 x 2 =x1. x2 x1 . x2

XOR:

Y is 1 if only one variable is 1 and the other is zero

x1

x1x2

0
0
1
1

0
1
0
1

0
1
1
0

x2
y
x1
x2

XNOR:

x1
x2

XOR

x1x2

y =x1 e x 2 = x1. x2 x1 . x2

Y is 1 if only both variables are either 0 or 1

x1
x2

XNOR

y =x1 e x 2 =x1 x2
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AND: y =

Gates with more than 2 inputs

x1
x2
AND
x1. x 2 . x3 ...
x3

OR: y = x1 + x 2 x3 ....

x1
x2
x3

XOR: y =x1 x 2 x 3 = x1. x2 x3 x1 . x2 .x3 x1 . x2 .x3 x1.x2 .x3

Y = 1 only if odd number of inputs is 1

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Implementing Boolean expressions using gates

x

S x. y.z x. y.z x. y.z x. y.z

C x. y x.z y.z

y
z

x
y

x
x y z

z
y
z

x y z

z
S

x
y

y
z

x y z

x
y
z

x y z

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Implementing gates using Switches

Voltage controlled Switch
SN:
Switch is closed if voltage x is HIGH
Switch is open if voltage x is LOW

x
SN

Voltage controlled Switch

SP:
Switch is closed if voltage x is LOW
Switch is open if voltage x is HIGH

x
SP

We have seen earlier (in class 12) that transistors act as switches !
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SN

SP

Switch is closed if voltage x is HIGH

Switch is open if voltage x is LOW

Switch is closed if voltage x is LOW

Switch is open if voltage x is HIGH

VDD = 5V
closed
SP

x
LOW

HIGH
1

0
SN

open

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NOT gate

48

NAND Gate

NAND:

y = x1 . x 2

VDD = 5V

x1

SP

x2

SP

x1
y

x1

LOW

x2

LOW HIGH

LOW HIGH HIGH

SN

HIGH LOW HIGH

HIGH HIGH LOW

x2

SN

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NOR Gate

NOR: y = x1 + x 2

VDD = 5V

x1

x1

SP

LOW
x2

x2

LOW HIGH

LOW HIGH LOW

SP

HIGH LOW

LOW

HIGH HIGH LOW

x1

SN

x2

SN

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Design Overview
a
b
c

Full Adder

a b

c S CY

0 0 0 0 0

0 0 1 1 0

CY

0 1 0 1 0
0 1 1 0 1
1 0 0 1 0

S x. y.z x. y.z x. y.z x. y.z

1 0 1 0 1
1 1 0 0 1

C x. y x.z y.z

1 1 1 1 1
VDD = 5V

x
y

S
x y z

z
x

x y z

x1

x2

y
z

x2

SP

SP
y

x y z

SP

x1

x y z

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SN

SN

SN
51

SOP AND POS

REPRESENTATIONS
Electronics - I, The LNM Institute of
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52

Representation of Boolean Expressions

y f1

y min term

0
0
1
1

0
1
0
1

0
0
1
1

0
1
0
1

0
1
1
0

f1 = m1 m2

f1 = x . y x. y
f 2 = (0, 2,3) ?

x.y
x.y
x.y
x.y

m0
m1
m2
m3

f1 = (1, 2)

f 2 = x . y x. y x . y

A minterm is a product that contains all the variables used in a function

Electronics - I, The LNM Institute of
Information Technology, Jaipur

53

Three variable functions

y z min terms

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z

m0
m1
m2
m3
m4
m5
m6
m7

f 2 = (1, 4, 7) ?
f 2 = x . y. z x. y. z x . y . z
Electronics - I, The LNM Institute of
Information Technology, Jaipur

54

Product of Sum Terms Representation

y f1

0
0
1
1

0
1
0
1

0
0
1
1

0
1
1
0

F1 = (x+y)(x + y)

= M0.M3

y Max term
0
1
0
1

x+y
x+y
x+y
x+y

M0
M1
M2
M3

= M0M3

Electronics - I, The LNM Institute of

Information Technology, Jaipur

55

x
0
0
0
0
1
1
1
1

y z Max. terms
0
0
1
1
0
0
1
1

0 x + y + z M0
1 x + y + z M1
0 x + y + z M2
1 x + y + z M3
0 x + y + z M4
1 x + y + z M5
0 x + y + z M6
1 x + y + z M7

f1 = (1,5, 7) ?
f 2 = (x y z ).( x y z ).( x y z )
Electronics - I, The LNM Institute of
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56

Simplification of Boolean Expressions

x1 x2 x3 y
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
0
1
0
1
0
1

y= (1,3,5, 7)
y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3
x1
x2
x3
x1
x2
x3
x1

x2
x3
x1
x2
x3

Simplification of Boolean expression yields : y = x3 !! which does not

require any gates at all ! Electronics - I, The LNM Institute of
Information Technology, Jaipur

57

Goal of Simplification

y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3

x1
x2
x3
x1
x2
x3

x1
x2
x3
x1
x2
x3

Goal of simplification is to reduce the complexity of gate circuit. This requires

that we minimize the number of gates. Since number of gates depends on
number of minterms, one of the goals of simplification is to minimize the
number of minterms in SOP expression
Electronics - I, The LNM Institute of
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58

y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3

y = x1 . x3 x1. x2 . x3 x1. x2 . x3

x1
x2

x1

x3

x3

x1
x2
x3
x1
x2
x3
x1
x2
x3

x1

x2
x3
x1
x2
x3

This circuit is simpler not just because it uses 4 gates instead of 5 but also
because circuit-2 uses one 2-input and three 3-input gates as compared to five
3-input gates used in circuit-1

Electronics - I, The LNM Institute of

Information Technology, Jaipur

59

Goal of Simplification
In the SOP expression:

1. Minimize number of product terms

2. Minimize number of literals in each term

Simplification Minimization

Electronics - I, The LNM Institute of

Information Technology, Jaipur

60

Minimization

y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3

y = x1 . x3 .( x2 x2 ) x1. x3 .( x2 x2 )
y = x1 . x3 x1. x3
y =( x1 x1 ). x3

y = x3
Principle used: x + x = 1
Electronics - I, The LNM Institute of
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61

f = x . y x. y x . y
Apply the Principle: x + x = 1 to simplify
f = x .( y y ) x . y
f = x x. y

How do we simplify further?

f = x . y x. y x . y x . y x . y x. y x . y
Principle used : x + x = x

f = x . y x. y x . y x . y
x . ( y y ) ( x x). y x y
Electronics - I, The LNM Institute of
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62

Simplify

f x1. x2 . x3 . x4 x1. x2 . x3 . x4 x1. x2 . x3 . x4 x1. x2 . x3 . x4

x1. x2 . x3 . x4 x1. x2 . x3 . x4

Principle: x + x = 1 and x + x = x

Need a systematic and simpler method for applying these two principles

Karnaugh Map (K map) is a popular technique for carrying out simplification

It represents the information in problem in such a way that the two

principles become easy to apply

Electronics - I, The LNM Institute of

Information Technology, Jaipur

63

KARNAUGH MAPS
Electronics - I, The LNM Institute of
Information Technology, Jaipur

64

K-map representation of truth table

x
0
0
1
1

y min term
0
1
0
1

x.y
x.y
x.y
x.y

y f1

0
0
1
1

0
1
0
1

0
1
1
0

m0
m1
m2
m3

y
x
0

m0

m1

m2

m3

x
0

Electronics - I, The LNM Institute of

Information Technology, Jaipur

65

f 2 = (0, 2,3)

y
x
0

f = x .y x . y

Electronics - I, The LNM Institute of

Information Technology, Jaipur

66

3-variable K-map representation

x

y z min terms

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

x
0
0
0
0
1
1
1
1

0
1
0
1
0
1
0
1

x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z
x.y.z

y z
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

m0
m1
m2
m3
m4
m5
m6
m7

yz

01

11

10

m0

m1

m3

m2

m4

m5

m7

m6

f
0
1
0
1
0
1
0
1

00

yz

00

01

11

10

Electronics - I, The LNM Institute of

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67

yz

00

01

11

10

f = x.y . z x. y . z x. y . z x. y . z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

68

4-variable K-map representation

w x

z min terms

0 0 0 0

m0

0 0 0 1

m1

0 0 1 0

m2

0 0 1 1

m3

1 1 1 0

m14

1 1 1 1

m15

yz
wx 00
00 1

01

11

10

01

11

10

yz
wx 00
00 0

01

11

10

01

11

12

13

15

14

10

11

10

f =w. x . y . z w. x . y . z w. x . y . z w. x . y . z
w . x . y . z w . x . y. z w . x . y . z
Electronics - I, The LNM Institute of
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69

Minimization using Kmap

f 2 = (2,3)

f = x. y x . y

y
x
0

f = x.( y y )
f= x
Combine terms which differ in only one bit position. As a result,
whatever is common remains.

Electronics - I, The LNM Institute of

Information Technology, Jaipur

70

y
x
0

y
x
0

f = x. y x . y

f=y

f = ( x. x). y

x
0

f=y

Electronics - I, The LNM Institute of

Information Technology, Jaipur

f =x
71

y
x
0

f = x. y x . y x . y

f = x.( y y ) x . y
x x. y

f = x x. y x. y
x ( x x). y
x y
The idea is to cover all the 1s with as few and as simple terms as possible
Electronics - I, The LNM Institute of
Information Technology, Jaipur

72

3-variable minimization

yz

00

01

11

10

f = x .y . z x . y . z x . y . z x . y . z

y. z

x. z
f = x .y . z y . z x . z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

73

3-variable minimization

yz

00

01

11

10

f = x .y . z x . y . z x . y . z x . y . z
x. z

x. z
f = x . z x. z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

74

3-variable minimization

yz

00

01

11

10

f = x. y . z x . y . z x . y . z x . y . z

f =x . y x . y

x. y
x. y
x

yz

00

01

11

10

f =x .( y y ) x

Electronics - I, The LNM Institute of

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75

yz

00

01

11

10

yz

00

01

11

10

00

01

11

10

00

01

11

10

yz

yz

f =x z
Electronics - I, The LNM Institute of
Information Technology, Jaipur

x
76

Can we do this ?

yz

00

01

11

10

Note that each encirclement should represent a single product term. In this
case it does not.

f =x . y. z x. y.z x. y.z
x . y x.z

We do not get a single product term.

In general we cannot make groups of 3 terms.
Electronics - I, The LNM Institute of
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77

Can we use kmap with the following ordering of variables?

yz

00

01

10

11

Can we combine these two terms into a single term ?

f =x . y. z x. y.z
x .( y. z y.z )
Note that no simplification is possible.
Kmap requires information to be represented
Electronics - I, The LNM Institute of
Information Technology, Jaipur

78

yz

00

01

10

11

These two terms can be combined into a single term but it is not easy to
show that on the diagram.

f = x . y. z x. y.z
x .( y y ).z x.z
Kmap requires information to be represented in such a way that it is easy
to apply the principle
x x1
Electronics - I, The LNM Institute of
Information Technology, Jaipur

79

4-variable minimization
yz
wx 00
00 1

01

11

10

01

11

10

w. y . z

w. x . z

w. y . z
f = w . y. z w . x. z w . y. z w . x . y. z w . x . y. z
But is this the simplest expression ?
Electronics - I, The LNM Institute of
Information Technology, Jaipur

80

yz
wx 00
00 1

01

11

10

yz
wx 00
00 1

01

11

10

01

01

11

11

10

10

w. x . y . z w. x . y . z w. x . z

w. x . y . z w. x . y . z x . y . z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

81

4-variable minimization
yz
wx 00
00 1

x. y. z

01

11

10

01

11

10

w. y . z

w. x . z

w. x . z

w. y . z
f = w . y. z w . x. z w . y. z w . x . z x . y. z
Is this the best that we can do ?
Electronics - I, The LNM Institute of
Information Technology, Jaipur

82

Cover the 1s with minimum number of terms

yz
wx 00
00 1

01

11

10

yz
wx 00
00 1

01

11

10

01

01

11

11

10

10

f = w . y. z w . x. z

f = w . y. z w . x. z

w . y. z w . x . z x . y. z

w . x . z x . y. z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

83

4-variable minimization
yz
wx 00
00 1

01

11

10

yz
wx 00
00 1

01

11

10

01

01

11

11

10

10

f = w . x. y w. x. z w . y. z

f = w . x. y w. x. z x . y. z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

84

Groups of 4

yz
wx 00
00 0

y.z

01

11

10

01

11

10

01

11

10

yz
wx 00
00 0
01

11

10

Electronics - I, The LNM Institute of

Information Technology, Jaipur

w. x

x. z
w. z
85

yz
wx 00
00 0

01

11

10

yz
wx 00
00 0
01

01

11

10

11

01

11

10

01

11

10

10

yz
wx 00
00 1

x. z

01

11

10

yz
wx 00
00 1
01

11

10

01

11

10

x. z

Electronics - I, The LNM Institute of

Information Technology, Jaipur

x. z

??

86

Groups of 8
yz
wx 00
00 0

01

11

10

01

11

10

01

11

10

01

11

10

01

11

10

yz
wx 00
00 1

yz
wx 00
00 0

01

11

10

01

11

10

yz
wx 00
00 1

01

11

10

Electronics - I, The LNM Institute of

Information Technology, Jaipur

87

Examples
yz
wx 00
00 0

01

11

10

yz
wx 00
00 0

01

11

10

01

01

11

11

10

10

Electronics - I, The LNM Institute of

Information Technology, Jaipur

88

Dont care terms

y0
y1
y2
y3

a
Decimal
Decoder

b
c
d

Y3

y9

a b c

d y0y1y2y3y4y5y6y7y8y9

0 0 0 0 1000000000
0 0 0 1 0100000000
0 0 1 0 0010000000
0 0 1 1 0001000000
0 1 0 0 0000100000

cd
ab 00
00 0

0 1 0 1 0000010000

01

11

10

0 1 1 0 0000001000

0 1 1 1 0000000100
1 0 0 0 0000000010

01

11

1 0 1 0

xxxxxxxxxx

1 0 1 1

10

1 1 0 0

xxxxxxxxxx
xxxxxxxxxx

1 1 0 1

xxxxxxxxxx

1 1 1 0

xxxxxxxxxx

1 1 1 1

xxxxxxxxxx

y3 a.b.c.d

1 0 0 1 0000000001

Electronics - I, The LNM Institute of

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89

Dont care terms can be chosen as 0 or 1.

Depending on the problem, we can choose the dont care term
as 1 and use it to obtain a simpler Boolean expression

Y3

cd
ab 00
00 0

01

11

10

01

11

10

y3 b.c.d
Dont care terms should only be included in encirclements if it helps in
obtaining a larger grouping or smaller number of groups.
Electronics - I, The LNM Institute of
Information Technology, Jaipur

90

Minimization of Product of Sum Terms using Kmap

y
x
0

y
x
0

f = x y

f = x x. y x. y
x ( x x). y
x y

y
x
0

Electronics - I, The LNM Institute of

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f=y
91

y
x
0

y
x
0

f =x

f=y
x

x. z

yz

00

01

11

10

f =( x . z ).( x z )
Electronics - I, The LNM Institute of
Information Technology, Jaipur

xz

f = x . z x. z
92

x yz

yz
wx 00
00 0

01

11

10

01

11

10

x yz

w y z
w x

f =( x y z ).( x y z ).( w y z ).( w x)

Electronics - I, The LNM Institute of
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93

Example
Obtain the minimized PoS by suitably using dont care terms

yz
wx 00
00 1

01

11

10

01

11

10

f =( x w z ).( x w y ).( y z )
Electronics - I, The LNM Institute of
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94

Design Flow

System Description

system

x
0
0
0
0
1
1
1
1

Truth Table

y z
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

f
0
1
0
1
0
1
0
1

Boolean Expression

f = x.y . z x. y . z x. y . z x. y . z
Minimized
Boolean Expression

f = x . z x. z
x
y
y

Electronics - I, The LNM Institute of

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Gate Netlist

z
x
z

95

Mapping of Boolean expression to a Network of

gates available in the library
x1
x2

y = x1 . x2 . x3 x1. x2 . x3 x1. x2 . x3 x1. x2 . x3

x3
x1
x2
x3

x1
x2
x3
x1
x2
x3

Library of available Gates

Cost

Inverter

Two input NAND

Three input NAND

AND-OR-Invert

Y AB C

Electronics - I, The LNM Institute of

Information Technology, Jaipur

3
96

IMPLEMENTATION USING
SPECIFIC GATES
Electronics - I, The LNM Institute of
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97

Implementation using only NAND gates

x. y

x. x x

x. y

f = x. y x y

A SoP expression is easily implemented with NAND gates. f =a.b c.d g .h

a

h
Electronics - I, The LNM Institute of
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98

c
f

a
b
c
d

g
h

There is a one-to-one mapping between AND-OR network and NAND network

Electronics - I, The LNM Institute of
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99

Often there is lot of further optimization that can be done

Consider implementation of XOR gate f A .B A. B

f A .B B.B A. B A. A
B ( A B ) A( A B )

Electronics - I, The LNM Institute of

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100

Implementation using only NOR gates

xx x

x y

x y

f = x y x. y

To implement using NOR gates, it is easiest to start with minimized Boolean

expression in POS form

f =(a b).(c d ).( g h)

Electronics - I, The LNM Institute of

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101

f =(a b).(c d ).( g h)

a

c
f

a
b
c
f

d
g
h

There is a one-to-one mapping between OR-AND network and NOR network

Electronics - I, The LNM Institute of
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102

To implement SoP expression using NOR gates, determine first the

corresponding PoS expression and then follow the procedure
outlined earlier

Implement f(x,y,z) = x . z x . z using NOR gates

x

yz

00

01

11

10

0
x

z
x
z

f =( x . z ).( x z )

Similarly PoS expression can be implemented as NAND network by first

converting it to SoP expression and then following the procedure outlined
earlier
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103

COMBINATIONAL CIRCUIT
DESIGN
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104

Digital Circuits

Combinational Circuits

Sequential Circuits
X

CC

X
CC

W
Storage
elements

Output is determined by current

values of inputs only.

Output is determined in general

by current values of inputs and
past values of inputs/outputs as
well.

Electronics - I, The LNM Institute of

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105

Design of Complex Combinational circuits

A(0:7)

S(0:7)
8-bit adder

B(0:7)

A7A6...A0

B7B6...B0 S7S6...S0 C

00...0

00...0

00...0

00...1

00...0

00...1

00...0

00...1

00...1

System
Description

Truth
Table

Boolean
expression

Truth table has 216 entries

Minimized Boolean
expression

Gate
Netlist

This design approach becomes difficult to use

Electronics - I, The LNM Institute of
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106

Design system as a network of sub-systems that are of

manageable size and can be implemented using the
earlier approach of truth table, minimization etc.
A(0:7)

1101

S(0:7)

+ 1110

8-bit adder
B(0:7)

11011
a b c S CY

C7

S7

C1

S1

C0

S0

0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1

1-bit adder

1-bit adder

1-bit adder

1 0 0 1 0
1 0 1 0 1
1 1 0 0 1

B7

A7

B1

A1

B0

A0

Electronics - I, The LNM Institute of

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1 1 1 1 1

107

General Approach
Sub-system-1
Sub-system-2

System
Sub-system-3

There are certain sub-systems or blocks that are used quite often such as :
1.
2.
3.
4.
5.
6.

decoders, encoders
Multiplexers
Adder/Subtractors, Multipliers
Comparators
Parity Generators
..
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108

Decoders
Maps a smaller number of inputs to a larger set of outputs in general

B
A
B

2-to-4 line
decoder

y0

0 0 1

0 0 0

y1

0 1 0

1 0 0

1 0 0

0 1 0

1 1 0

0 0 1

y2
y3

y0
A
B

2-to-4 line
decoder

A Y0 Y1 Y2 Y3

y1
y2
y3

a Y0 Y1 Y2 Y3

0 0 0

1 1 1

0 1 1

0 1 1

1 0 1

1 0 1

1 1 1

1 1 0

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- I, The LNM Institute of
Active
Low
Information Technology, Jaipur

109

Example
M-1

M-1

M-2

2-to-4
decoder

M-2

M-3

M-3

M-4

M-4

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110

Decoder with Enable Input

2/4

y0
y1
y2

A
B

y3

2/4

y0
y1
y2

A
B

y3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

0 0 0 1

0 0 0

0 0 1 0

1 0 0

0 1 0 0

0 1 0

0 1 1 0

0 0 1

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111

Decoder: gate Implementation

E

2/4

y0
y1
y2

A
B

y3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

Y0 =E.B.A ; Y1 =E.B.A ; Y2 =E.B.A ; Y3 =E.B.A

E.B.A

Y0
A

E.B.A
Y1

E.B.A
Y2
B

E.B.A
Y3

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112

A n to 2n decoder is a minterm generator

E .B.A
E

y min term

0
0
1
1

0
1
0
1

x.y
x.y
x.y
x.y

Y0

E .B.A

m0
m1
m2
m3

Y1

E .B.A

Y2

E.B.A

Y3

It can be used to implement any combinational circuit

B A f1
0
0
1
1

0
1
0
1

0
1
1
0

2/4
1

1
0

y0
y1
y2

A
B

y3

0
1
0
0

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113

Implementation of a 3-variable function with a 3-to-8 decoder

C B A

0
0
0
0
1
1
1
1

1
0
1
0
1
0
0
0

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

3/8
0

0
0
0

A
B
C

y0
y1
y2
y3
y4
y5
y6
y7

0
1
1
1
1
1
1
1

Although it is easy to implement any combinational circuit with this method ,

it is often very inefficient in terms of gate utilization. Note that this method
does not require any minimization.
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Implementing larger decoders using simpler ones.

3/8 decoder using 2/4 decoders

3/8
E

A
B
C

y0
y1
y2
y3
y4
y5
y6
y7

2/4

C
0

2/4

y0
y1
y2

A
B
E

y3
2/4

y4
y5
y6

A
B

y7

How many 2/4 decoders are required to implement a 4/16 decoder ?

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115

E C B A y0

y1 y2 y3 y4 y5 y6 y7

0 x x x

0 0 0 0

0 0 0

1 0 0 0

1 0 0 0

0 0 0

1 0 0 1

0 1 0 0

0 0 0

1 0 1 0

0 0 1 0

0 0 0

1 0 1 1

0 0 0 1

0 0 0

1 1 0 0

0 0 0 0

0 0 0

1 1 0 1

0 0 0 0

1 0 0

1 1 1 0

0 0 0 0

0 1 0

1 1 1 1

0 0 0 0

0 0 1

1
0
A
B

2/4

E
0

C
0

2/4

y0 0
y1 1
y2 0
y3 0

2/4

y4 0
0
y5
y 0
6

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

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A
B

y7 0

116

Seven segment decoder

a

a
f

b
c
d
e
f
g

b
g

d
a

b
g

c
d

5
5
5
5
5

D
C
B

7-segment
decoder

(abcdefg)

5
0
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117

Seven segment decoder

a
f

D
b

C
B

7-segment
decoder

(abcdefg)

BA
DC 00
00 1

01

11

10

01

11

10

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118

D
C
B

7-segment
decoder

(abcdefg)

A
BL

7449 BCD to seven segment decoder

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119

Encoders
An encoder performs the inverse operation of a decoder.
d3

4/2
0

1
2
3

d 1d 0
d3d2 00
00
01

01
0

11

10
1

11
10

d2 d1 d0 B A

0 0

1 0 0

0 1

0 0 1

1 0

0 1 0

0 0

0 1 1

d 1d 0
d3d2 00
00
01

01
0

11

10
0

B d1 d 0

11
1

A d2 d0

10

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120

M-1

M-1

M-2

M-2

2-to-4
decoder

M-3

M-3

M-4

M-4
M-1

4/2
encoder

2/4
decoder

M-2

M-3

M-4
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121

Priority Encoders
D0

Priority is 3,2,1,0 with user 3

having the highest priority

printer

D1
D2

Resource

4:1 MUX

X, Y have to be determined
based on this priority order and
the requests to use the resource.

D3
x
R0
R1
R2
R3

y
priority
Encoder

R1R0
R3R2 00
00 0

R 1R 0
R3R2 00

R0

R1 R2 R3 x

0 0

0 0

0 0 0

01

01

1 0

0 0 1

11

11

0 1 0

10

10

1 1 1

01

11

10

x R2 R3

00

Y
01

11

10

y R1 R2 R3

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122

Gray Codes
decimal

Natural
Binary

Gray

0000

0000

0001

0001

0010

0011

0011

0010

0100

0110

0101

0111

0110

0101

0111

0100

1000

1100

1001

1101

10

1010

1111

11

1011

1110

12

1100

1010

13

1101

1011

14

1110

1001

15

1111

1000

In the case of natural binary code:

0111-1111-1000

0111-0000-1000

In the case of Gray code, no such

problem occurs.

1-bit change as one goes from

one code word to the next.

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ASCII: American Standard Code for information interchange

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124

Parity
Extra bits are added to aid in error detection and correction

decimal

Binary

Even
parity

Odd
parity

000

0000

0001

001

0011

0010

010

0101

0100

011

0110

0111

100

1001

1000

101

1010

1011

110

1100

1101

111

1111

1110

A 1-bit error changes the parity and thus can be detected

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125

Multiplexers

I0

2:1
mux

I1

I0

I1

I0

I0

1
I1

I0
0

Y0

0
0
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126

I0

00

I1
I2

01 4:1
10 mux

I3

11

S 1 S0

0 0

I0

0 1

I1

1 0

I2

1 1

I3

S1 S 0
S0

S1

I0

I1

I2

I3
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127

Mux is often used when resources have to be shared

a(0:7) b(0:7) c(0:7) d(0:7)

S 1 S0 y =

S1

1
c

S2

0 0 a+c
0 1 a+d
1 0 b+c
1 1 b+d

8-bit ader
= a+c

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128

Implementing Boolean expressions using Multiplexers

y x1 x2 x1 x2

x2

x2

0
y
1

x1
x1 x2

y = x2 when x1 = 0
y = x2 when x1 = 1

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129

F ( x, y, z ) (1, 2, 6, 7)
A 3 variable function can be implemented with a 4:1 mux with 2 select lines

x
0

00

x
1

01
10

11
y

z F

0 0

1
0

0 0
0 1

0
1

1
0

0 1
1 0

0
1

1 0

1 1 0

1 1 1

F = 0 when yz = 00
F = x when yz =01
F = 1 when yz = 10

F = x when yz = 11

Mux is more efficient way of implementing combinational circuits as

compared to decoders.
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130

Mux. expansion

E
I0

I1

E S
y

S1

1 0

I0

1 1

I1

I0

I1

I1

S0 1

S 1 S0

0 0

I0

0 1

I1

1 0

I2

1 1

I3

I2

I3

I1
0

S0

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131

Mux. expansion

E
I0

I1

E S
y

S1

I1

1 0

I0

1 1

I1

I0

S0

S1 S0

0 0

I0

0 1

I1

1 0

I2

1 1

I3

I2

I3

I3
I3
1

S0

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132

DeMultiplexer

u-1

u-11

u-1

u-2

u-22

u-2

u-11

u-22

Demux

Mux
u-3

u-33

u-3

u-4

u-44

u-4

Data x
S1
S0

0
1
2
3

u-33

u-44

S1 S0 y0 y1 y2 y3
0 0

0 1

0 0 0
0 x 0 0

1 0

0 0

0
x
1
1
0
0
0
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133

Demultiplexer is very much like a decoder

E

Data

S0

A
B

Dmux

S1 S0 y0 y1 y2 y3
0 0

0 1

0 0 0
0 x 0 0

1 0

0 0

1 1

0
0 0 0 x

y3

E B

A Y0 Y1 Y2 Y3

x 0

0 0 0

1 0 0 1

0 0 0

1 0 1 0

1 0 0

1 1 0 0

0 1 0

1 1 1 0

0 0 1

Data
Y0

S0

0
S1

y0
y1
y2

0
1
2
3

S1

2/4

Data

Y1

Y1

Y2

Y0

Y2
B

Y3

Y3

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134

Comparator
A(0:3)

B(0:3)

A<B
4-bit
comparator

A>B

A3A2A1A0 B3B2B1B0 A<B A>B A=B

0000

0000

0000

0001

0001

0000

A=B

a
b
a<b

a
b

1-bit
comparator

a>b

a>b

a=b

a<b

a
b
a=b
a
b

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a3<b3

a3
b3

1-bit
comparator

a3>b3
a3=b3

a2<b2

a2
b2

1-bit
comparator

a2>b2
a2=b2

a1<b1

a1
b1

A>B

1-bit
comparator

a1>b1
a1=b1

a0<b0

a0
b0

1-bit
comparator

A=B

a0>b0
a0=b0

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136

Adder/Subtractor
S

Half Adder

a b

0 0

0 0

0 1

1 0

1 0

1 0

1 1

0 1

S a.b a.b ; C a.b

a b Cin S Cout
0 0 0 0 0
0 0 1 1 0

0 1 0 1 0

111
110

0 1 1 0 1

Cout

Full Adder

Cin

1 0 0 1 0
1 0 1 0 1

1111

1 1 0 0 1

1 1 1 1 1

S a.b.cin a.b.cin a.b.cin a.b.cin ; Cout a.b a.cin b.cin

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137

S Cin (a b)

S a.b.cin a.b.cin a.b.cin a.b.cin

Cout a.b a.Cin b.Cin

Cout Cin (a.b a.b) a.b Cin .(a b) a.b

ab

Cin (a b)
S

Cin .(a b)
a.b
Cout
Cin

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138

4-bit Adder

S(0:3)

Cout

A 3A 2A 1A 0 B 3B 2B 1B 0 S 3S 2S 1S 0

4-bit adder

C 3 C 2 C1

Cout

0000

0000

0000

0000

0001

0001

0001

0000

0001

A 3 A 2 A 1A 0
B 3 B 2 B 1B 0

C 4 S 3 S 2 S 1S 0
A(0:3)

B(0:3)

S3
C4

C2

C3

FA

FA

A3

B3

S0

S1

S2

A2

C1

FA

B2

A1

B1

0
FA

A0

B0

Ripple Carry Adder (20 gate circuit)

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139

Subtraction
A - B = A + 2s complement of B
A - B = A + 1s complement of B+1
A - B = A + B+1

FA

FA

FA

B3
A3

FA

B2
A2

B1
A1

B0

A0

1
B3

B2

B1

B0

One needs add a circuit for predicting errors resulting from overflow
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140

Adder/Subtractor

FA

A3

FA

B3

A2

FA

B2

A1

FA

B1

A0

FA

B0

A3

FA

FA

A2

FA

A1

A0
1

B3

FA

A3

FA

B2

FA

A2

B1

B0

FA

A1

A0
M=1

B3

B2

B1

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B0
141

Multiplier

B1

B0

A1

A0

A0B1

C3

A1B1

A1B0

C2

C1

multiplicand
multiplier

A0B0
Partial products

C0

A0
A1

B0

B1

HA

C3

B1

B0

HA

C2

C1

C0

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SEQUENTIAL CIRCUITS
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Digital Circuits

Combinational Circuits

Sequential Circuits
X

CC

X
CC

Storage
elements

Output is determined by current

values of inputs only.

Output is determined in general

by current values of inputs and
past values of inputs/outputs as
well.

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NOR SR Latch

S
1

Q 1; Q 0 Set State
Q 0; Q 1 Re set State

Q
0

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State
SET

145

NOR SR Latch
Reset
R

Q 1; Q 0 Set State
Q 0; Q 1 Re set State

Set
S

SET

RESET

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State

146

HOLD State
R

S
1

SET

RESET

Q
0

State

HOLD
INVALID

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Both the outputs are well defined and

0. the first problem is that we do not
get complementary output.

A more serious problem occurs when we switch the latch to the hold state by
changing RS from 11 00 .
Suppose the inputs do not change
simultaneously and we get the situation 11 01* 00

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Q=1

148

R 1

R 0

0
Q

Q
S

1
Q

0
Q

Q=1
Suppose the inputs change as RS = 11 10* 00
R

0
Q

Q=0
So although output is well defined when we apply RS = 11, it becomes
unpredictable once we switch the latch to hold state by applying RS = 00. That
is why RS = 11 is not used as an input combination.
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The error can occur also due to unequal gate delays.

1
1

0
1

Q
S

0
0

Q=1

Suppose gate-1 is faster

On the other hand suppose that gate-2 is faster.
R

1
1

0
1

0
1

Q
S

Again the output is unpredictable in general

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Q=0
150

NAND Latch
S

S
0

SET

RESET

Q
1

State

HOLD
INVALID

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RS NAND Latch with Enable

S

EN

Hold State

0
1

Q
EN

1
R

Enable

S R

Q Q

x x

Q Q

Hold

1 0

1 0

Set

0 1

0 1

Reset

0 0

Q Q

Hold

1 1

0 0

Invalid

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State

152

D latch

1
1

EN
R

S R

Q Q

x x

Q Q

Hold

1 0

1 0

Set

0 1

0 1

Reset

0 0

Q Q

Hold

1 1

0 0

Invalid

EN
0

Enable

S
R

State

EN

If EN = 1 then Q = D otherwise the latch is in Hold state

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Synchronous Sequential Circuits

X

CC

Storage
elements
n

Clock

Data (x)

Data is stable when clock is high

X(n)

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Example

an

bn 0
cn

0
0

zn
0
yn

clk

Clock

an
bn
cn

y
z

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Example

an

bn 1
cn

1
0 1

1 0

zn 0
0 1
yn

clk

Clock

an
bn
cn

y
z

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Problem with Latch

1

zn

1
D
clk

yn

Circuits are designed with the idea there

would be single change in output or
memory state in single clock cycle.

clk
y
z

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157

Edge Triggered Latch or Flip-flop

clk

Clock

Positive edge triggered flipflop

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Negative Edge Triggered Latch or Flip-flop

clk

Clock

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Master-Slave D Flip-flop
D

slave

master
EN

EN

clk

Clock

Master
Slave

clk

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Positive edge triggered Flip-flop

1

10
5

0 1
Q

0 1
clk

1
3

1
D

Q
1 0

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Positive edge triggered Flip-flop

1

1
5

1
clk

1
3

1 0
D

0 1

A change in input has no effect if it occurs after the clock edge

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Positive edge Triggered Flip-flop with Asynchronous Reset

1

1
S

clk
3

clk
R

0
Reset
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Characteristic table
Given a input and the present state of the flip-flop,
what is the next state of the flip-flop
D

Inputs (D)

clk

Q(t+1)

Q(t 1) D
JK Flip-flop
J

Inputs J

KQ(t+1)

0 Q(t)

1 Q(t)

clk
K

Q(t 1) Q(t ).J Q(t ).K

Characteristic equation

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Toggle or T Flip-flop

Inputs (T)

clk

Q(t+1)

Q(t)

Q(t)

Q(t 1) Q(t ).T Q(t ).T

Excitation Table What inputs are required to effect a particular state change
Inputs
Q(t)

Q(t+1)

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Excitation Table

clk
K

Q(t+1)

Q(t)

Q(t)

Inputs
Q(t+1)

Q(t)

Inputs

D
clk

Q
D

Q(t+1)

Q(t+1)

Q(t)

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Convert a D FF to JK FF

CC

clk

JK
Q 00

01

11

10

Q(t+1)

Q(t)

Q(t)

Q(t)

Q(t)

D
J

clk
Q

D Q.J Q.K
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