INTEGRATED CIRCUITS

DESIGN &
APPLICATIONS
Fall 2017
Instructor
Assoc. Prof. Ahmed
Yahya

Text Book

Introduction
Integrated circuits: many transistors on one chip.
Very Large Scale Integration (VLSI): bucketloads!
Complementary Metal Oxide Semiconductor
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip
CMOS transistors
Building logic gates from transistors
Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip

Introduction

CMOS VLSI Design 4th Ed.

Systems and Chips

This course: designing ICs

Part of a system: chips + board + software +

System companies: HP, Cisco
Chip companies: Intel, Qualcomm
nVidia vs. Hercules
Example: high-end data switch
Marketing gives range of specs, architect tries to
meet them
Off the shelf chips, embedded software
Why dont we teach system design?
Introduction

CMOS VLSI Design 4th Ed.

Course Goals
Learn to design and analyze state-of-the-art digital
VLSI chips using CMOS technology
Employ hierarchical design methods
Understand design issues at the layout, transistor,
logic and register-transfer levels
Use integrated circuit cells as building blocks
Use commercial design software in the lab
Understand the complete design flow
Wont cover architecture, solid-state physics,
analog design
Superficial treatment of transistor functioning
Introduction

CMOS VLSI Design 4th Ed.

What Will We Cover?

Designing chips containing lots of transistors
How basic components work (transistors, gates,
flops, memories, adders, .)
Complexity management: hierarchy and CAD tools
Key issues:
Creating logical structures from transistors
Performance analysis and optimization
Testing: functional and manufacturing
Power consumption, clocking, I/O, etc.

Introduction

CMOS VLSI Design 4th Ed.

General Principles
Technology changes fast => important to understand
general principles
optimization, tradeoffs
work as part of a group
leverage existing work: programs ,building blocks
Concepts remain the same:
Example: relays -> tubes -> bipolar transistors
-> MOS transistors

Introduction

CMOS VLSI Design 4th Ed.

Types of IC Designs
IC Designs can be Analog or Digital
Digital designs can be one of three groups
Full Custom
Every transistor designed and laid out by hand
ASIC (Application-Specific Integrated Circuits)
Designs synthesized automatically from a high-level
language description
Semi-Custom
Mixture of custom and synthesized modules

Introduction

CMOS VLSI Design 4th Ed.

MOS Technology Trends

Introduction

CMOS VLSI Design 4th Ed.

Annual Sales

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CMOS VLSI Design 4th Ed.

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Corollaries
Since the cost of the printing process (called wafer
fabrication) is growing at a slower rate, it implies that
the cost per function, is dropping exponentially.
At each new generations, each gate cost about 1/2
what it did 1.5 years ago. Shrinking an existing chip
makes it cheaper!

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CMOS VLSI Design 4th Ed.

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Steps in Design
Designer

Tasks

Tools

Define Overall Chip

Architect

Text Editor
C Compiler

C/RTL Model
Initial Floorplan
Behavioral Simulation

Logic
Designer

Logic Simulation
Synthesis
Datapath Schematics

RTL Simulator
Synthesis Tools
Timing Analyzer
Power Estimator

Cell Libraries
Circuit
Designer

Circuit Schematics
Circuit Simulation
Megacell Blocks

Schematic Editor
Circuit Simulator
Router

Layout and Floorplan

Physical
Designer

Place and Route

Parasitics Extraction
DRC/LVS/ERC

Introduction

Place/Route Tools
Physical Design
and Evaluation
Tools

CMOS VLSI Design 4th Ed.

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System on a Chip
Source: ARM

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CMOS VLSI Design 4th Ed.

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Laboratory Design Tools

We will use commercial CAD tools
Cadence, Synopsys, etc.
Commercial software is powerful, but very complex
Designers sent to long training classes
Students will benefit from using the software, but we
dont have the luxury of long training
TAs have experience with the software
Start work early in the lab
Unavailability of workstations is no excuse for
exercises submissions.
Plan designs carefully and save work frequently
Introduction

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Need for transistors

Cannot make logic gates with voltage/current source,
RLC components
Consider steady state behavior of L and C
Need a switch: something where a (small) signal
can control the flow of another signal

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CMOS VLSI Design 4th Ed.

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Coherers and Triodes

Hertz: spark gap transmitter, detector
Verified Maxwells equations
Not practical Tx/Rx system
Marconi: coherer changes resistance after EM
pulse, connects to solenoid

Triode: based on Edisons bulbs!

See Ch. 1, Tom Lee, Design of CMOS RF ICs
Introduction

CMOS VLSI Design 4th Ed.

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A Brief History of MOS

Some of the events which led to the invention of
microprocessor
Photographs from State of the Art: A photographic
history of the integrated circuit, Augarten, Ticknor &
Fields, 1983.
They can also be viewed on the Smithsonian web
site, http://smithsonianchips.si.edu/

Introduction

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Silicon Lattice
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors

Introduction

Si

Si

Si

Si

Si

Si

Si

Si

Si

CMOS VLSI Design 4th Ed.

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Dopants
Silicon is a semiconductor
Pure silicon has no free carriers and conducts
poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)

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Dopants

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CMOS VLSI Design 4th Ed.

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p-n Junctions
A junction between p-type and n-type semiconductor
forms a diode.
Current flows only in one direction

Introduction

p-type

n-type

anode

cathode

CMOS VLSI Design 4th Ed.

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nMOS Transistor
Four terminals: gate, source, drain, body
Gate oxide body stack looks like a capacitor
Gate and body are conductors
SiO2 (oxide) is a very good insulator
Called metal oxide semiconductor (MOS)
capacitor
Even though gate is
no longer made of metal*

* Metal gates are returning today!

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nMOS Transistor

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nMOS Operation
Body is usually tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF

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nMOS Operation Cont.

When the gate is at a high voltage:
Positive charge on gate of MOS capacitor
Negative charge attracted to body
Inverts a channel under gate to n-type
Now current can flow through n-type silicon from
source through channel to drain, transistor is ON

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pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior

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pMOS Transistor

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Power Supply Voltage

GND = 0 V
In 1980s, VDD = 5V
VDD has decreased in modern processes
High VDD would damage modern tiny transistors
Lower VDD saves power
VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,

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Transistors as Switches
We can view MOS transistors as electrically
controlled switches
Voltage at gate controls path from source to drain
d
nMOS

pMOS

g=1

d
OFF

ON

OFF

ON
s

Introduction

g=0

CMOS VLSI Design 4th Ed.

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CMOS Inverter
A

0
1

OFF
ON
ON
OFF

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CMOS NAND Gate

A

OFF
ON
OFF
ON

A
B

Introduction

1
0
0
1
0
1

CMOS VLSI Design 4th Ed.

OFF
ON

Y
ON
OFF
OFF
ON
OFF
ON

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CMOS NOR Gate

A

Introduction

A
B
Y

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3-input NAND Gate

Y pulls low if ALL inputs are 1
Y pulls high if ANY input is 0

A
B
C
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CMOS Fabrication
CMOS transistors are fabricated on silicon wafer
Lithography process similar to printing press
On each step, different materials are deposited or
etched
Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process

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Inverter Cross-section
Typically use p-type substrate for nMOS transistors
Requires n-well for body of pMOS transistors

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Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD
Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps

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Inverter Mask Set

Transistors and wires are defined by masks
Cross-section taken along dashed line

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Detailed Mask Views

Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal

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Fabrication
Chips are built in huge factories called fabs
Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

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Fabrication Steps
Start with blank wafer
Build inverter from the bottom up
First step will be to form the n-well
Cover wafer with protective layer of SiO2 (oxide)
Remove layer where n-well should be built
Implant or diffuse n dopants into exposed wafer
Strip off SiO2

p substrate

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Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

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Photoresist
Spin on photoresist
Photoresist is a light-sensitive organic polymer
Softens where exposed to light

Photoresist
SiO2

p substrate

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Lithography
Expose photoresist through n-well mask
Strip off exposed photoresist

Photoresist
SiO2

p substrate

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Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

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Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step

SiO2

p substrate

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n-well
n-well is formed with diffusion or ion implantation
Diffusion
Place wafer in furnace with arsenic gas
Heat until As atoms diffuse into exposed Si
Ion Implanatation
Blast wafer with beam of As ions
Ions blocked by SiO2, only enter exposed Si
SiO2
n well

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Strip Oxide
Strip off the remaining oxide using HF
Back to bare wafer with n-well
Subsequent steps involve similar series of steps

n well
p substrate

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Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers)
Chemical Vapor Deposition (CVD) of silicon layer
Place wafer in furnace with Silane gas (SiH4)
Forms many small crystals called polysilicon
Heavily doped to be good conductor

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Polysilicon Patterning
Use same lithography process to pattern polysilicon

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Self-Aligned Process
Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact

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N-diffusion
Pattern oxide and form n+ regions
Self-aligned process where gate blocks diffusion
Polysilicon is better than metal for self-aligned gates
because it doesnt melt during later processing

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N-diffusion cont.
Historically dopants were diffused
Usually ion implantation today
But regions are still called diffusion

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N-diffusion cont.
Strip off oxide to complete patterning step

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P-Diffusion
Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact

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Contacts
Now we need to wire together the devices
Cover chip with thick field oxide
Etch oxide where contact cuts are needed

Contact

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Metalization
Sputter on aluminum over whole wafer
Pattern to remove excess metal, leaving wires

Metal

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Layout
Chips are specified with set of masks
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so
Normalize for feature size when describing design
rules
Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
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Simplified Design Rules

Conservative rules to get you started

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Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2sometimes called 1 unit
In f = 0.6 m process, this is 1.2 m wide, 0.6 m
long

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Summary

MOS transistors are stacks of gate, oxide, silicon

Act as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors

Now you know everything necessary to start

designing schematics and layout for a simple chip!

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