ARM

The first encounter

What Is ARM?
Advanced RISC Machine
First RISC microprocessor
for commercial use
Market-leader for low-power
and cost-sensitive embedded applications

ARM Powered Products

Features
Architectural simplicity
which allows
Very small implementations
which result in
Very low power consumption

The History of ARM

Developed at Acorn Computers Limited,
of Cambridge, England,
between 1983 and 1985
Problems with CISC:
Slower then memory parts
Clock cycles per instruction

The History of ARM (2)

Solution the Berkeley RISC I:
Competitive
Easy to develop (less than a year)
Cheap
Pointing the way to the future

ARM Architecture
Typical RISC architecture:
Large uniform register file
Load/store architecture
Simple addressing modes
Uniform and fixed-length instruction fields

ARM Architecture (2)

Enhancements:
Each instruction controls the ALU and shifter
Auto-increment
and auto-decrement addressing modes
Multiple Load/Store
Conditional execution

ARM Architecture (3)

Results:
High performance
Low code size
Low power consumption
Low silicon area

Pipeline Organization
Increases speed
most instructions executed in single cycle
Versions:

3-stage (ARM7TDMI and earlier)

5-stage (ARMS, ARM9TDMI)

6-stage (ARM10TDMI)

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Pipeline Organization (2)

3-stage pipeline: Fetch Decode - Execute
Three-cycle latency,
one instruction per cycle throughput
i
n
s
t
r
u
c
t
i
o
n

Fetch
i+1

Decode

Execute

Fetch

Decode

Execute

i+2

Fetch

Decode

Execute
cycle

t+1

t+2

t+3

11t+4

Pipeline Organization (3)

5-stage pipeline:

Reduces work per cycle =>

allows higher clock frequency

Separates data and

instruction memory =>
reduction of CPI
(average number
of clock Cycles Per Instruction)

Stages:
Fetch
Decode
Execute
Buffer/data
Write-back
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Pipeline Organization (4)

Pipeline flushed and refilled on branch,
causing execution to slow down
Special features in instruction set
eliminate small jumps in code
to obtain the best flow through pipeline

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Operating Modes
Seven operating modes:

User

Privileged:
System (version 4 and above)
FIQ
IRQ
Abort

exception modes

Undefined
Supervisor
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Operating Modes (2)

User mode:

Normal program
execution mode
System resources
unavailable
Mode changed
by exception only

Exception modes:

Entered
upon exception
Full access
to system resources
Mode changed freely

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Exceptions
Exception

Mode

Priority

IV Address

Reset

Supervisor

0x00000000

Undefined instruction

Undefined

0x00000004

Software interrupt

Supervisor

0x00000008

Prefetch Abort

Abort

0x0000000C

Data Abort

Abort

0x00000010

Interrupt

IRQ

0x00000018

Fast interrupt

FIQ

0x0000001C

Table 1 - Exception types, sorted by Interrupt Vector addresses

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ARM Registers
31 general-purpose 32-bit registers
16 visible, R0 R15
Others speed up the exception process

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ARM Registers (2)

Special roles:

Hardware
R14 Link Register (LR):
optionally holds return address
for branch instructions
R15 Program Counter (PC)

Software
R13 - Stack Pointer (SP)
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ARM Registers (3)

Current Program Status Register (CPSR)
Saved Program Status Register (SPSR)
On exception, entering mod mode:

(PC + 4) LR

CPSR SPSR_mod

PC IV address

R13, R14 replaced by R13_mod, R14_mod

In case of FIQ mode R7 R12 also replaced

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ARM Registers (4)

System & User

FIQ

Supervisor

Abort

IRQ

Undefined

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)

R0
R1
R2
R3
R4
R5
R6
R7_fiq
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R15 (PC)

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_svc
R14_svc
R15 (PC)

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_abt
R14_abt
R15 (PC)

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_irq
R14_irq
R15 (PC)

R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13_und
R14_und
R15 (PC)

CPSR

CPSR
SPSR_fiq

CPSR
SPSR_svc

CPSR
SPSR_abt

CPSR
SPSR_irq

CPSR
SPSR_und

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Instruction Set
Two instruction sets:

ARM
Standard 32-bit instruction set

THUMB
16-bit compressed form
Code density better than most CISC
Dynamic decompression in pipeline

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ARM Instruction Set

Features:

Load/Store architecture

3-address data processing instructions

Conditional execution

Load/Store multiple registers

Shift & ALU operation in single clock cycle

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ARM Instruction Set (2)

Conditional execution:

Each data processing instruction

prefixed by condition code

Result smooth flow of instructions through pipeline

16 condition codes:

EQ

equal

MI

negative

HI

unsigned
higher

GT

signed greater
than

NE

not equal

PL

positive or
zero

LS

unsigned
lower or same

LE

signed less
than or equal

CS

unsigned
higher or
same

VS

overflow

GE

signed greater
than or equal

AL

always

CC

unsigned
lower

VC

no overflow

LT

signed less
than

23NV

special
purpose

ARM Instruction Set (3)

ARM instruction set

Data processing
instructions
Block transfer
instructions
Multiply instructions

Data transfer
instructions
Branching instructions
Software interrupt
instructions

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Data Processing Instructions

Arithmetic and logical operations
3-address format:

Two 32-bit operands

(op1 is register, op2 is register or immediate)
32-bit result placed in a register

Barrel shifter for op2 allows full 32-bit shift

within instruction cycle
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Data Processing Instructions (2)

Arithmetic operations:

ADD, ADDC, SUB, SUBC, RSB, RSC

Bit-wise logical operations:

AND, EOR, ORR, BIC

Register movement operations:

MOV, MVN

Comparison operations:

TST, TEQ, CMP, CMN

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Data Processing Instructions (3)

Conditional codes

+
Data processing instructions

+
Barrel shifter

=
Powerful tools for efficient coded programs
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Data Processing Instructions (4)

e.g.:

if (z==1) R1=R2+(R3*4)
compiles to
EQADDS R1,R2,R3, LSL #2
( SINGLE INSTRUCTION ! )
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Data Transfer Instructions

Load/store instructions
Used to move signed and unsigned
Word, Half Word and Byte to and from registers
Can be used to load PC
(if target address is beyond branch instruction range)
LDR

Load Word

STR

Store Word

LDRH

Load Half Word

STRH

Store Half Word

LDRSH

Load Signed Half Word

STRSH Store Signed Half Word

LDRB

Load Byte

STRB

LDRSB

Load Signed Byte

STRSB Store Signed Byte

Store Byte
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Block Transfer Instructions

Load/Store Multiple instructions
(LDM/STM)
Whole register bank
or a
subset
copied to memory or restored
with single instruction

LDM
R0

Mi
Mi+1
Mi+2

R1
R2
Mi+14
Mi+15
R14

STM

R15
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Swap Instruction
Exchanges a word
between registers
Two cycles
but
single atomic action
Support for RT
semaphores

R0
R1
R2

R7
R8

R15

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Modifying the Status Registers

Only indirectly

R0
R1

MSR moves contents

from CPSR/SPSR
to selected GPR
MRS moves contents
from selected GPR
to CPSR/SPSR

MRS
R7
CPSR
SPSR

MSR

R8

R14
R15

Only in privileged
modes
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Multiply Instructions
Integer multiplication (32-bit result)
Long integer multiplication (64-bit result)
Built in Multiply Accumulate Unit (MAC)
Multiply and accumulate instructions add product
to running total

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Multiply Instructions
Instructions:
MUL

Multiply

32-bit result

MULA

Multiply accumulate

32-bit result

UMULL

Unsigned multiply

64-bit result

UMLAL

Unsigned multiply accumulate

64-bit result

SMULL

Signed multiply

64-bit result

SMLAL

Signed multiply accumulate

64-bit result

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Software Interrupt
SWI instruction

Forces CPU into supervisor mode

Usage: SWI #n
31

28 27
Cond

24 23
Opcode

0
Ordinal

Maximum 224 calls

Suitable for running privileged code and
making OS calls

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Branching Instructions
Branch (B):
jumps forwards/backwards
up to 32 MB
Branch link (BL):
same + saves (PC+4) in LR
Suitable for function call/return
Condition codes for conditional branches
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Branching Instructions (2)

Branch exchange (BX) and
Branch link exchange (BLX):
same as B/BL +
exchange instruction set (ARM THUMB)
Only way to swap sets

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Thumb Instruction Set

Compressed form of ARM

Instructions stored as 16-bit,

Decompressed into ARM instructions and
Executed

Lower performance (ARM 40% faster)

Higher density (THUMB saves 30% space)
Optimal
two sets)

interworking (combining
compiler supported
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THUMB Instruction Set (2)

More traditional:

No condition codes

Two-address data processing instructions

Access to R0 R8 restricted to

MOV, ADD, CMP

PUSH/POP for stack manipulation

Descending stack (SP hardwired to R13)

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THUMB Instruction Set (3)

No MSR and MRS,
must change to ARM to modify CPSR
(change using BX or BLX)
ARM entered automatically after RESET
or entering exception mode
Maximum 255 SWI calls

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The Next Step

New ARM Cortex family of processors

New NEON media and

signal
processing extensions
Thumb-2 blended 16/32-bit instruction set
for performance and low power
Improved Interrupt handling

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Summary
Adoption of ARM technology
has increased efficiency and lowered costs
ARM is the worlds leading architecture today

3 billion ARM Powered chips and counting

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References
www.arm.com
ARM Limited ARM Architecture Reference Manual,
Addison Wesley, June 2000
Trevor Martin The Insiders Guide To The Philips ARM7Based Microcontrollers, Hitex (UK) Ltd., February 2005
Steve Furber ARM System-On-Chip Architecture
edition), Addison Wesley, March 2000

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(2nd

The End
Authors:
Nemanja Perovic, [email protected]
Prof. Dr. Veljko Milutinovic, [email protected]

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