5 RTL Verilog Behavioral Assign
5 RTL Verilog Behavioral Assign
aAb
addr1[20:17] + addr2[20:17]
ini | in2
Operands
any one of the data types:-
integers, real, registers, nets, times
examples :-
integer count, finalcount;
real a, b, c;
c = a - b; // a and b are real operands
4 < = 3 // result is 0
4 > 3 // result is 1
2blx >= 2bll // result is x
Equality operators
logical-equality (==), logical-inequality (!=)
case-equality (===), case-in-equality (!==)
comparison is bit by bit
zero filling if unequal length
If used in expression
returns 1 if expression is true
returns 0 if expression is false
for (==) and (!=), returns x if x or z in operand
for (===) and (!==), only returns 1 or 0
4 == 3 // result is 0
4b1010 != 4b1101 // result is 1
4b101x == 4b101x // result is x
4b101x === 4b101x // result is 1
4b101z != 4b101z//result isx
4b101z !== 4b101z // result is 0
Bitwise operators
negation (~), and (&), or (|), xor (A), xnor (A~, ~A)
comparison is bit by bit
zero filling if unequal length
z is treated as x
4'b1001 //result is 1
Shift operators
right shift (>>), left shift (<<)
shift a vector operand by specified number of bits
the vacant bit positions are filled with zeros
shift operations do not wrap around
> cout
a >
HA > sum
b >
endmodule
Example 2 : 1-bit Full Adder
Design a 1-bit Full adder based on continuous assignment
c n
> cout
a >
> FA > sum
b