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Single and Double Precision Floating Point Multiplication and Division Alu

This document describes the design of a floating point arithmetic logic unit (ALU) that performs single and double precision floating point multiplication and division. It includes representations of floating point numbers in single and double precision IEEE 754 formats, as well as algorithms and block diagrams for floating point multiplication and division. The ALU uses a pipelined structure with four stages - operand checking, exponent operations, fraction operations, and normalization/rounding.

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64 views26 pages

Single and Double Precision Floating Point Multiplication and Division Alu

This document describes the design of a floating point arithmetic logic unit (ALU) that performs single and double precision floating point multiplication and division. It includes representations of floating point numbers in single and double precision IEEE 754 formats, as well as algorithms and block diagrams for floating point multiplication and division. The ALU uses a pipelined structure with four stages - operand checking, exponent operations, fraction operations, and normalization/rounding.

Uploaded by

reneeshcz
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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SINGLE AND DOUBLE PRECISION

FLOATING POINT MULTIPLICATION


AND DIVISION ALU

Reneesh C Zacharia
Reg. no 2882122

Internal Guide: Mr. T RAVI ME ,(Ph.D )


GOAL OF THE PROJECT
 Implementation of double precision floating point
multiplication and division
 Implementation of pc interface of single precision
floating point multiplication and division
INTRODUCTION

 The system is a 32-bit floating point ALU.


 The system can be expected to perform 32-bit
multiplication and division operations.
 The system use four levels of pipelining.

 The floating point numbers are represented in


IEEE-754 standard.
REPRESENTATION OF FLOATING POINT NUMBERS IN
SINGLE PRECISION IEEE 754 STANDARD
SIGN EXPONENTIAL MAGNITUDE

31 30-23 22-0
IEEE 754 SINGLE PRECISION
Bits of precision 24
Unbiased exponent Emax 127
Unbiased exponent Emin -126
Exponent bias 127
REPRESENTATION OF FLOATING POINT NUMBERS IN
SINGLE PRECISION IEEE 754 STANDARD
 

Value = N = (-1)S X 2 E-127 X (1.M)


SIGN EXPONENTIAL MAGNITUDE

31 30-23 22-0
REPRESENTATION OF FLOATING POINT NUMBERS IN
DOUBLE PRECISION IEEE 754 STANDARD
SIGN EXPONENTIAL MAGNITUDE

63 62-52 51-0
IEEE 754 DOUBLE PRECISION
Bits of precision 53
Unbiased exponent Emax 1023
Unbiased exponent Emin -1022
Exponent bias 1023
REPRESENTATION OF FLOATING POINT NUMBERS IN
DOUBLE PRECISION IEEE 754 STANDARD
 

Value = N = (-1)S X 2 E-1023 X (1.M)


SIGN EXPONENTIAL MAGNITUDE

63 62-52 51-0
ARITHMETIC UNIT DESIGN STRUCTURE
LOGIC UNIT DESIGN STRUCTURE
ADVANTAGES OF PIPELINING
 It can accept a new instruction every clock cycle

 The cycle time of the processor is reduced, thus


increasing instruction issue-rate in most cases.

 Some combinational circuits such as adders or


multipliers can be made faster by adding more circuitry.
If pipelining is used instead, it can save circuitry
DESCRIPTION-DOUBLE PRECISION (64-BIT)

• The 64-bit floating point numbers are stored in four


pipelined registers.
• There are four pipelined units. They perform
following functions in parallel.
1. ‘0’ operation number check
2. Exponent addition and subtraction operation
3. Fraction multiplication and division operation
4. Result normalization and rounding
BASIC FLOATING POINT MULTIPLICATION ALGORITHM

• Assuming that the operands are already in the IEEE


754 format, performing floating point multiplication:
• Result = R = X * Y = (-1)Xs (Xm x 2Xe) * (-
1)Ys (Ym x 2Ye)
involves the following steps:

(1) If one or both operands is equal to zero, return


the result as zero, otherwise:
 
(2) Compute the sign of the result Xs XOR Ys

(3) Compute the mantissa of the result:


• Multiply the mantissas: Xm* Ym
• Round the result to the allowed number of mantissa bits

(4) Compute the exponent of the result:


Result exponent = biased exponent (X) + biased exponent
(Y) - bias

(5) Normalize if needed, by shifting mantissa right,


incrementing result exponent.
 
MULTIPLICATION FLOW CHART
BASIC FLOATING POINT DIVISION ALGORITHM

 Assuming that the operands are already in the IEEE


754 format, performing floating point multiplication:
  

 Result = R = X / Y = (-1)Xs (Xm x 2Xe) /


(-1)Ys (Ym x 2Ye)
 involves the following steps:

(1) If the divisor Y is zero return “Infinity”, if both are


zero return “NaN”
(2) Compute the sign of the result Xs XOR Ys

(3) Compute the mantissa of the result:

The dividend mantissa is extended to 48 bits by adding 0's to


the right of the least significant bit.

When divided by a 24 bit divisor Ym, a 24 bit quotient is produced.

(4) Compute the exponent of the result:


 
Result exponent = [biased exponent (X) - biased exponent (Y)] +
bias
DIVISION FLOW CHART
FIRST STAGE OF CONNECTION GRAPH

OPERAND CHECKING MODULE


SECOND STAGE

EXPONENT ADDITION AND SUBTRACTION MODULE


THIRD STAGE

FRACTION MULTIPLICATION AND DIVISION MODULE


FOURTH STAGE

NORMALIZATION AND ROUNDING MODULE


PC INTERFACE

FUNCTIONAL BLOCKS OF PC INTERFACE


RESULTS-32 BIT
RESULT-64 BIT
REFERENCES
 ‘Computer Organization’ by Carl Hamacher
 Verilog HDL –Samir Palnikar
 VLSI Digital Signal Processing Systems-Keshab K.parhi
 Fundamental of Digital Design –Floyed
 IEEE Standard of Binary Floating-Point
Arithmetic" IEEEStandard754,IEEE Computer
Society,1985
 Design of Double Precision IEEE-754 Floating-Point
Units by Michael Kennedy B.I.T -Griffith University
THANK YOU

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