UNIT 5: CENTRAL PROCESSING UNIT

Introduction

General Register Organization

Stack Organization

Instruction Formats

Addressing Modes

Reduced Instruction Set Computer

CPU

Register Set

CU

ALU

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General Register Organization
Input
R1
R2
R3
R4
R5
R6
R7

LD SELA MUX MUX SELB

3x8 A bus B bus

Decoder
OPR
ALU
SELD
Example: R1 R2 + R3
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 Control

OPERATION OF CONTROL UNIT

Example: R1 R2 + R3

[1] MUX A selector (SELA): BUS A R2

[2] MUX B selector (SELB): BUS B R3
[3] ALU operation selector (OPR): ALU to ADD
[4] Decoder destination selector (SELD): R1 Out Bus

Encoding of register selection fields

Binary
Code SELA SELB SELD
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2
011 R3 R3 R3
100 R4 R4 R4
101 R5 R5 R5
110 R6 R6 R6
111 R7 R7 R7
 General Register Organization
Input
OPR Operation R1

00000 Add A + B R2
R3
00011 Subtract A B R4
00100 Transfer A R5
00101 Increment A R6
R7
00110 Decrement A
01000 AND A and B LD SELA MUX MUX SELB
01010 OR A and B
3x8 A B
01100 XOR A and B Decoder
01110 Complement A OPR
ALU
10000 Shift right A SELD

11000 Shift left A

Examples: Microoperation SELA SELB SELD OPR

R1 R2 R3 010 011 001 00011
R4 SHL R4 100 000 100 11000
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Homework

Chapter 8

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 Homework
8-3 Specify the control word that must be applied to the
processor of Fig. 8-2 to implement the following micro
operations.
a. R1 R2 + R3
b. R4 R4
c. R5 R5 1
d. R6 shl R1
e. R7 input

3 3 3 5
Control Word : SELA SELB SELD OPR

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8-3
 Homework
8-4 Determine the micro operations that will be executed in
processor of Fig 8.2 in the following 14 bit control world
are applied .
a. 001 010 011 00101
b. 000 000 000 00000
c. 010 010 010 01100
d. 000 001 000 00010
e. 111 100 011 10000

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8-4
 8.1
A bus-organized CPU similar to Fig.8-2 has 16 registers with
32 bits in each, an ALU, and a destination decoder.
a. How many selection inputs are needed for MUX A and
MUX B?
b. How many inputs and outputs are there in the decoder?
c. How many inputs and outputs are there in the ALU for data,
including input and output carries?
d. Formulate a control word for the system assuming that the
ALU has 35 operations.

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8.1

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 Stack Organization

LIFO Current
Last In First Out Top of Stack
TOS 63

6
5
SP 4 0 1 2 3
3 0 0 5 5
FULL EMPTY 2 0 0 0 8
1 0 0 2 5
Stack Bottom 0 0 0 1 5
Stack
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 Stack Organization

PUSH Current 1 6 9 0
SP SP + 1 Top of Stack
TOS 63
M[SP] DR
If (SP = 64) then (FULL 1)
EMPTY 0 6
5 1 6 9 0
SP 4 0 1 2 3
3 0 0 5 5
FULL EMPTY 2 0 0 0 8
1 0 0 2 5
Stack Bottom 0 0 0 1 5
Stack
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 Stack Organization

POP Current
DR M[SP] Top of Stack
TOS 63
SP SP - 1
If (SP = 0) then (EMPTY 1)
FULL 0 6
5 1 6 9 0
SP 4 0 1 2 3
3 0 0 5 5
FULL EMPTY 2 0 0 0 8
1 0 0 2 5
Stack Bottom 0 0 0 1 5
Stack
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 Stack Organization

Memory Stack
PC 0
PUSH
1
SP SP + 1 2
M[SP] DR
AR 100
POP
101
DR M[SP] 102

SP SP - 1
200
SP 201
202

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 Reverse Polish Notation

Infix Notation
A+B

Prefix or Polish Notation

+AB

Postfix or Reverse Polish Notation (RPN)

AB+
(2) (4) (3) (3) +
RPN (8) (3) (3) +
24+33 2433+
(8) (9) +
17
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 Reverse Polish Notation

Example
(A + B) [C (D + E) + F]

(A B +) (D E +) C F +

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 Reverse Polish Notation

Stack Operation
(3) (4) (5) (6) +

PUSH 3
PUSH 4
6
MULT
PUSH 5 30
4
5
PUSH 6
3
42
12
MULT
ADD

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 CPU Organization
Single Accumulator
ADD x

General Register
ADD R1, R2
ADD R1, R2, R3

Stack
PUSH x
ADD
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 Instruction Formats

Three-Address Instructions
ADD R1, A , B R1 M[A] + M[B]
Two-Address Instructions
ADD R1, A R1 R1 + M[A]
One-Address Instructions
ADD M AC AC + M[AR]
Zero-Address Instructions
ADD TOS TOS + (TOS 1)
RISC Instructions
Lots of registers. Memory is restricted to Load & Store
LOAD R1, A
LOAD R2, B
ADD R1, R1, R2 20 / 44
 Instruction Formats

Example: Evaluate (A+B) (C+D)

Three-Address
1. ADD R1, A, B ; R1 M[A] + M[B]
2. ADD R2, C, D ; R2 M[C] + M[D]
3. MUL X, R1, R2 ; M[X] R1 R2

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 Instruction Formats

Example: Evaluate (A+B) (C+D)

Two-Address
1. MOV R1, A ; R1 M[A]
2. ADD R1, B ; R1 R1 + M[B]
3. MOV R2, C ; R2 M[C]
4. ADD R2, D ; R2 R2 + M[D]
5. MUL R1, R2 ; R1 R1 R2
6. MOV X, R1 ; M[X] R1

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 Instruction Formats

Example: Evaluate (A+B) (C+D)

One-Address
1. LOAD A ; AC M[A]
2. ADD B ; AC AC + M[B]
3. STORE T ; M[T] AC
4. LOAD C ; AC M[C]
5. ADD D ; AC AC + M[D]
6. MUL T ; AC AC M[T]
7. STORE X ; M[X] AC

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 Instruction Formats

Example: Evaluate (A+B) (C+D)

Zero-Address
1. PUSH A ; TOS A
2. PUSH B ; TOS B
3. ADD ; TOS (A + B)
4. PUSH C ; TOS C
5. PUSH D ; TOS D
6. ADD ; TOS (C + D)
7. MUL ; TOS (C+D)(A+B)
8. POP X ; M[X] TOS 24 / 44
 Instruction Formats

Example: Evaluate (A+B) (C+D)

RISC
1. LOAD R1, A ; R1 M[A]
2. LOAD R2, B ; R2 M[B]
3. LOAD R3, C ; R3 M[C]
4. LOAD R4, D ; R4 M[D]
5. ADD R1, R1, R2 ; R1 R1 + R2
6. ADD R3, R3, R4 ; R3 R3 + R4
7. MUL R1, R1, R3 ; R1 R1 R3
8. STORE X, R1 ; M[X] R1 25 / 44
 Homework
8-9 Convert the following numerical arithmetic expression
into reverse Polish notation and show the stack operations
for evaluating the numerical result.
(3 + 4) [10 (2 + 6) + 8]

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8-9

6
 Homework
8-12 Write a program to evaluate the arithmetic statement.

a. Using general register computer with three address instruction

b. Using general register computer with two address instruction
c. Using accumulator type computer with one address instruction
d. Using stack organized computer with zero address instruction

RPN:

XAB CDE * F * + GHK * + / =

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 8-12

(a)Three address instruction:

SUB R1,A,B
MUL R2,D,E
SUB R2,R2,F
MUL R2,R2,C
ADD R1,R1,R2
MUL R2,H,K
ADD R2,R2,G
DIV X,R1,R2
 8-12
(B)Two address instruction:
MOV R1,A
SUB R1,B
MOV R2,D
MUL R2,E
SUB R2,F
MUL R2,C
ADD R1,R2
MOV R2,H
MUL R2,K
ADD R2,G
DIV R1,R2
MOV X,R1
8-12
(C) One address instruction:
LOAD A
SUB B
STORE T
LOAD D
MUL E
SUB F
MUL C
ADD T
STORE T
LOAD H
MUL K
ADD G
STORE U
LOAD T
DIV U
STORE X
8-12

(D) RPN: XAB CDE * F * + GHK * + / = PUSH X

PUSH A
PUSH B
SUB
PUSH C
PUSH D
PUSH E
MUL
PUSH F
SUB
MUL
ADD
PUSH G
PUSH H
PUSH K
MUL
ADD
DIV
EQU
 Addressing Modes

Opcode Mode ...

Implied
AC is implied in ADD M[AR] in One-Address
instr.
TOS is implied in ADD in Zero-Address instr.

Immediate
The use of a constant in MOV R1, 5, i.e. R1 5

Register
Indicate which register holds the operand

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 Addressing Modes

Register Indirect
Indicate the register that holds the number of the
register that holds the operand
R1
MOV R1, (R2)

Auto increment / Auto decrement R2 = 3

Access & update in 1 instr. R3 = 5

Direct Address
Use the given address to access a memory location

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 Addressing Modes

Indirect Address
Indicate the memory location that holds the address of
the memory location that holds the data

AR = 101

100
101 0 1 0 4
102
103
104 1 1 0 A

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 Addressing Modes

Relative Address
EA = PC + IR(Address) 0
1
PC = 2 2

100
AR = 100
101
102 1 1 0 A
103
104

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 Addressing Modes

Indexed
EA = Index Register + AR(Address)

IR = 2

100
AR = 100
101
102 1 1 0 A
103
104

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 Addressing Modes

Base Register
EA = Base Register + AR(Address)

AR = 2

100 0 0 0 5
R1 = 100
101 0 0 1 2
102 0 0 0 A
103 0 1 0 7
104 0 0 5 9

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 Addressing Modes
Implied
Immediate
Register
Register Indirect
Auto increment / Auto decrement
Direct Address
Indirect Address
Relative Address
Indexed
Base Register
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 Addressing Modes

ADDRESSING MODES - EXAMPLES -

Address Memory
200 Load to AC Mode
PC = 200 201 Address = 500
202 Next instruction
R1 = 400

399 450
IR= 100 700
400
401 725
AC
500 800

600 900

Addressing Effective Content 702 325

Mode Address of AC
Direct address 500 /* AC (500) */ 800
Immediate operand - /* AC 500 */ 500 800 300
Indirect address 800 /* AC ((500)) */ 300
Relative address 702 /* AC (PC+500) */ 325
Indexed address 600 /* AC (IR+500) */ 900
Register - /* AC R1 */ 400
Register indirect 400 /* AC (R1) */ 700
Autoincrement 401 /* AC (R1)+ */ 725
Autodecrement 399 /* AC -(R) */ 450
 RISC

OVERLAPPED REGISTER WINDOWS

 RISC

OVERLAPPED REGISTER WINDOWS

R15
Common to D and A
R10
R73
Proc D Local to D
R64
R63
Common to C and D
R58
R57
Proc C Local to C
R48
R47
Common to B and C
R42
R41
Proc B Local to B
R32
R32 R31
Common to A and B
R26
R25
Proc A Local to A
R16
R15
Common to A and D
R10
R9
Common to all
procedures
R0
Global
registers
OVERLAPPED REGISTER WINDOWS
There are three classes of registers:
Global Registers(10 registers)
Available to all functions
Window local registers(10 registers)
Variables local to the function
Window shared registers(2set of 6 registers)
Permit data to be shared without actually needing to copy it

Only one register window is active at a time

The active register window is indicated by a pointer

When a function is called, a new register window is activated

This is done by incrementing the pointer
OVERLAPPED REGISTER WINDOWS

The advantage of overlapped register windows is

that the processor does not have to push registers
on a stack to save values and to pass parameters
when there is a function call
Conversely, pop the stack on a function return

This saves
Accesses - memory to access the stack.
The cost of copying the register contents at all

Since function calls and returns are so common, this

results in a significant savings relative to a stack-
based approach
OVERLAPPED REGISTER WINDOWS
Suppose proc A calls proc B.
Registers R26-R31 are common to both.
Proc A stores parameters for proc B in these registers.
At the end of proc B, it stores results to registers R26-R31.

Window size = L + 2C + G ------------10 + 12 + 10 = 32

Register file = (L + C)W + G..(10 + 6 )4 + 10= 74

No of global registers = G
No of registers in each window = L
No. of registers common to two windows = C
No of window = W
 CISC
Design of Instruction set for the processor

Complex Instruction Set Computer

Large number of instructions with a complicated ALU
Large variety of addressing modes (5-20)
Variable length instruction formats
Instructions can manipulate operands in memory

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 RISC

Reduced Instruction Set Computer

Relatively few instructions, hence simple ALU
Relatively few addressing modes
Memory access limited to load and store
All operations done within registers of the CPU
Fixed-length and easily decoded instruction format
Single-cycle instruction execution
Hardwired control unit

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 Types of Instructions

Data Transfer Instructions

Name Mnemonic
Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

Data Manipulation Instructions

Program Control Instructions
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 Data Manipulation Instructions

Arithmetic Name
Increment
Mnemonic
INC
Decrement DEC
Logical & Bit Manipulation Add ADD
Subtract SUB
Shift Multiply MUL
Divide DIV
Add with carry ADDC
Subtract with borrow SUBB
Name Mnemonic
Negate NEG
Clear CLR
Complement COM Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
Disable interrupt DI Rotate left through carry ROLC
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Program Control Instructions

Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Call CALL Carry bit, Sign bit,
Zero bit, Overflow bit
Return RET
Compare (Subtract) CMP
Test TST

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Status Bits
8-bit 8-bit

C7 = 1
A B

C8 =1 ALU
F0 to F7
V Z S C
F7 = 1

Zero Check

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 Questions of GTU
1. List the characteristics of RISC architecture & CISC architecture. (4 times)

2. Explain stack organization of Computer system? Explain push and pop

micro-operations. (2 times)

3. List the addressing modes. Explain any Three with example. (4-5 times)

4. What is overlapped register window? How window size and register file size
is computed? (4-5 times)

5. Convert (A + B) * [C * (D + E) +F] into prefix and postfix notation. (1 time)

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 Questions of GTU Conti
6. Convert the following into reverse polish notation.
1) A+B*[C*D+E*(F+G)]
2) A*[B+C*(D+E)] / [F+G*(H+I)] (2 times)

7. Explain Stack organization of Computer system and evaluate the

following expression using stack
(3+4)*[10(2+6)+8] (1 time)

8. What is the importance of status bits for program control? Which

types of status bits are stored in a status register? Explain it with block
diagram. (1 time)

9. Explain four types of instruction formats. (1 time)

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 Homework
8-7 Convert the following arithmetic expressions from infix to
reverse Polish notation.
a. A B + C D + E F
b. A B + A (B D + C E)
c. A + B [C D + E (F + G)]
A * [B + C (D + E)]
d.
F (G + H)

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 8-7
(a) A*B+C*D+E*F
RPN: AB * CD * EF * + +

(b) A*B+A*(B*D+C*E)
RPN: AB * ABD * CE * + * +

(c) A+B*[C*D+E*(F+G)]
RPN: FG+E*CD*+B*A+

(d) A*[B+C*(D+E)] / [F*(G+H)]

RPN: ABCDE + * + * FGH + */