UNIT 4

MEMORY SYSTEM

General Objective:
To know and understand the
memory system & design.
 OUTLINE
GENERAL OBJECTIVE

Understand Memory in Computer Systems

 The architecture of memory in a
computer system
There are two catagories of memory
i. primary and
ii. secondary
Primary memory is used as the internal memory, which
is in constant communication with the process of a
computer system.
Primary memory is also called internal memory, main
memory,working memory, and semiconductive memory
Primary memory are divided two type
i. RAM
ii. ROM
Figure shows Memory of computer
system

Computer

Internal
Internal
Memory
Memory
Arithmetic
Arithmetic Control
Control (semiconductor)
unit Unit (semiconductor)
unit Unit

Auxiliary mass
strorage
(tape, disk, MBM)
 secondary memory, which is separated
from the internal working memory
Secondary memory is also called mass
storage, it has the capacity to store
massive amounts of data without the need
for electrical power
secondary memory operates at a much
slower speed than internal memory
Typical secondary memory devices are
floppy disk, CD-ROM, magnetic disk,
magnetic tape
Figure shows the typical contents
of the two major memories.
Primary memory Secondary memory

ROM RAM Hard disk & other

auxiliary devices
Firmware Working Application software
Booting Storage -Words
Program -Excell
-etc

Transfared when necessary

Comparison of Primary and Secondary
memory

Primary Memory Secondary memory

internal memory of a external memory of a computer.
computer. Auxiliary memory
During program execution, the Harddisk
program and any data used by floppy disk
the program is resided. CDROM
RAM and ROM magnetic disk/tape.
Fast operation. mass storage
Main memory easily expanded.
Working memory stores programs and data that
Made of semiconductor are not currently being used by the
Smaller capacity CPU, only transferred when it is
Store Boot up program (BIOS) needed.
Store Firmware. Store application software such
as Microsoft Word.
 Types of memory
SEMICONDUCTOR
MEMORY

ROM RAM

PROGRAMABLE ERASABLE PROGRAMABLE SRAM DRAM

(RMM)

MROM PROM

UV ELECTRIC
ERASABLE ERASABLE

EPROM

EEPROM EAROM
 ROM (READ ONLY MEMORY)
The read only memory (ROM) is a type of semiconductor
memory.
It is designed to hold data that either are permanent or
will not change frequently.
During normal operations, no new data can be written
into a ROM but data can be read from
Since all ROMs are nonvolatile, these programs are not
lost when electrical power is turned off.
ROMs contributes to a broad class of semiconductor
memories design for application where the ratio of read
operation to write operation is very high (write very less,
read more ).
 MROM (MASK- Programmed ROM)
MROM but is normally referred as just ROM
only.
The mask programmed ROM, acronymed
MROM.
It has its storage location written into
(programmed) by the manufacturer according to
the customers specifications.
a photographic negative called a mask is used
to control the electrical interconnections on the
chip.
A major disadvantage of MROM is that it cannot
be reprogrammed
 PROM (Programmable ROM)
PROM is also programmed once but it is programmed by
the programmer not the factory.
A mask-programmed ROM is very expensive and would
not be used except in high volume applications, where
the cost would be spread out over many units.
For lower volume applications, manufacturers have
developed fusible-link PROMs that are user-
programmable; that is,
PROM is like an MROM in the way it cannot be erased
and reprogrammed.
These devices are often referred to as one time
programmable ROMs.
 EPROM
(Erasable Programmable ROM)
An EPROM can be programmed by a
user and it can also be erased and
reprogrammed as often as desired
the EPROM is a non-volatile memory that
will hold its stored data indefinitely as in
ordinary ROM
The process of programming an EPROM
involves the application of special voltage
levels (typically in the 10 to 25V range)
 EEPROM (Electrically erasable
PROM)
The disadvantage of the EPROM was overcome
by the development of the electrically erasable
PROM as an improvement over the EPROM
This modification produces the EEPROMs
major characteristics its electrical erasability.
the erasing and programming of an EEPROM
can be done in circuit
advantage of the EEPROM over the EPROM is
the ability to electrically erase and rewrite
individual bytes (8-bit words) in the memory
array
 EAPROM (Electrically Alterable
PROM)
EAPROM does not require the whole chip
to be erased, rather it allows data
alteration at user selected location
Erasing and reprogramming of data in
EAPROM is done on board
The alteration of data in the cell is done by
applying electrical pulse to them
RAM (Random Access Memory)
RAM is used in computer for the
temporary storage of programs and data
The contents of many RAM address
location will be read from and written to as
the computer executes a program.
A major disadvantage of RAM is that it is
volatile and will lose all stored information
if power is interrupted or turned off.
Comparison of SRAM and DRAM
SRAM DRAM
The main application of SRAMs the main internal memory of
are in areas where only small most personal microcomputer (e.g
amount of memory are needed 18M PC or APPLE ) uses DRAM
(up to 64 K), or
because of its high capacity
where high speed is required. and
Microprocessor controlled low power consumption.
instruments and appliances have These computer however,
very small memory capacity
sometimes use some small
requirements.
amounts of SRAM for functions
Some instruments, such as digital requiring maximum speed such
storage, oscilloscope and logic as video graphics and look-up
analyzers, require very high-speed tables.
memory, thus SRAM is normally
used.
 Pin connection of RAM
Memory chip is normaly recognized by its
memory capacity which has two main
elements i.e address size and data size

Address size : determine numbers

32k x 4
of address lines or bits (An)
4k x 8
Data size : determine numbers
2k x 8
of data lines / bits ( Dn)

Address Data
size size
 a) How to determine data lines
or pins?
From the chip capacity label, for instance
32 x 4 has a data size of 4 bits, means
each cell of the memory is sized 4 bits. In
orther words, this chip has 4 data
lines/pins which are labeled as Dn = D0,
D1, D2, D3.
 b) How to determine address
lines or pins?
From the chip capacity label as well, for instance 32 x 4
has a address size of 32 memory locations/cells (where
each cell has a data size of 4 bits ). Address size is
represented by equation of 2n, thus 2 n = 32 will give n
= 5. In other words, this memory has 5 address
lines/pins which are labeled as An = A0,A1, A2, A3, A4

2n = 32
log 2n = log 32
n log 2 = log 32
n = log 32
log 2
= 5
 What is the memory chip capacity in
bits?
Also from the chip capacity label, for instance 32
x 4, the chip capacity is:

Bit = 32 x 4 = 128 bits

Since 1 byte = 8 bits
Thus, capacity in byte is = 128 bits byte
8 bits
= 16 byte
 c) The control lines / pins :
Read / Write ( R/W ):
A same memory chip can be set to either
store in data (write) or withdraw data
(read), by applying a logic-1 or -0
respectively to its control pin labeled
The letter R with a bar on top ( R )
requires a logic- 0 at pin R/W to run READ
operation.
 Conti.
Contrary the letter W (without bar on top )
requires logic1 at pin R/W to run WRITE
operation.
READ : data is output from memory
Control line R/W = 0
WRITE : data is input into memory
Control line R/W = 1
 Conti..
Memory Enable (ME):
Each chip represents certain range of
address, need to set the only appropriate
chip to be made active, wheres the
others set inactive.
This is done by sending a logic to the
control pin ME, where logic0 inactivate
the chip and logic1 activate the chip.
ME = logic 1 = memory Enable
ME = logic 0 = memory Disable
 d) Pins layout of memory chip
After we have determined the pins of address,
data, and control lines, we may now compose
them into a block diagram of memory chip as
follows:
Input Data lines (4
bits)
We have: A4 D3 D2 D1 D0
Capacity = 32 x 4 Address A3 R/W Control
lines
Dn = D0,D1,D2,D3 (5 bits) A2 32 x 4 ME
lines

An = A0,A1,A2,A3,A4 A1

R/W A0 D3 D2 D1 D0

ME
Output data lines (4
bits)
 Outline
Introduction & Understand memory
Systems design
 Read Cycle
CPU sends a signal via control bus. If the
bus is busy, CPU is put on Wait state.
If the bus is free, CPU will place instruction
address on the address bus.
This address will be decoded or translated
by the circuitry in the memory or I/O
interface.
Finally the data at that specific address is
obtained, and is placed on the data bus.
Figure shows the the whole Read cycle in
the graphical form

Address Bus

SYSTEM
BUS
Data Bus

Control Bus

2 1
REQUEST

MEMORY
MPU Step 1 : Read Request
Step 2 : Send Address
RAM ROM
 Cont

Address Bus

SYSTEM
BUS
Data Bus

Control Bus

3 4

DATA TRANSFER
MEMORY MPU
Step 3 : Receive Data
RAM ROM Step 4 : Signal OK
 Write Cycle
Write cycle enables CPU sends data to
the memory or I/O devices.
CPU will send a signal (request to write) to
the control bus.
If the data bus is free, the data is placed
on the data bus, whereas the location
address will be placed on the address bus.
CPU will then send the data to the
destination with respect to the address.
Figure shows the whole Write cycle in the
graphical form

Address Bus

SYSTEM BUS
Data Bus

Control Bus

MEMORY MPU REQUEST

RAM ROM Step 1 : Write Request
 Cont.
2

Address Bus

SYSTEM BUS
3
Data Bus

Control Bus

MEMORY DATA TRANSFER

MPU
Step 2 : Send Address
RAM ROM Step 3 : Send Data
Step 4 : Signal OK
ADDRESS DECODER
(b) Two to form (2 to 4) decoder
 (c) Three to Eight ( 3 to 8 ) decoder

Figure shows the symbol and truth table of

a 3-to-8 decoder. It has n = 3 input bits,
which produces 2n = 23 = 8 bits of output.
For each input combination only one of the
8 output bit is active (logic-1) the other are
inactive (logic-0). In other words, the
similar relation of n inputs and 2n output is
applied to other capacity of decoder, such
as , 4 to 16; 5 to 32 and so on.
Figure The Two-to-Four (2-to-4) decoder
How to Design Address
decoder
 Cont..

ii. Now we need to determine the chip address

range: As shown in the memory mapping
section, for the fixed data size of 8 bits;
 Conti
iii). Determine address lines
Memory Block = 0000H 1FFFH
= 2000H
= 8192 location
 Cont.

iv). Draw out the address line tables:

 Cont.
v). Design Address decoder
From the above table :
(a) Since all chip has similar START / END address
bits for address lines : A10 Ao; thus A10 - A0 are the
common lines to all chips.
(b) Address lines that changes : A12 A11
We need two input decoders, however we use the
typical 74LS138 3 to 8 decoder. Thus we need the
two LSB bits A1, A0, to address four chips. Since
the start address is from 0000 H, thus the other
upper address lines A15 A13 are set logic-0 thus
we may set the MSB of decoder (A2) to logic-0.
Cont
 Cont.
vi). Draw out the complete memory circuit:
The complete memory circuit is illustrated in Figure Below:
(a) Each of the four memory chips is commonly connected to
- Address line A0 A10 (11 bits)
- Output data line Oo O7 ( for PROM).
If RAM is concerned : the unidirectional arrow will be
replaced by bidirectional arrow, and the output data pin
O0 O7 will be D1 D0.
(b) Address line A12 A11 as the input (A2,A1) to the 3-to-8
decoder 74LS138 whereas the A2 input of decoder is set logic
0. The output of decoder 0, 1, 2, 3, to the chip selected (CS)
pin of the four chips PROM-0, PROM 1, PROM 2, PROM
3 respectively.
Figure The complete memory circuit.
 MEMORY MAPPING
the capacity of a memory chip is
determined by the address size and data
size.
The memory of a computer system (which
is normally much greater than the capacity
of a single chip) is composed of many
memory chips with different address sizes
and data sizes, as shown in below
Memory is composed of many
single memory chips
 Example
For instance, a microprocessor has the
following characteristics:
a)CPU 8 bit data bus and 16 bit address bus
b)12 kbyte ROM
c)4 kbyte for I/O ports
d)16 kbyte RAM
 Address size = 2n = 2 16 = 65,536
location or cell (each has 8 bit data size)
Range of memory map
Memory map of 64K
(a). From START/END address to
determine block capacity.
(b). From block capacity to
START/END address