PowerPoint Slides

The
Processor
Language
Design
of Bits

Computer Organisation and Architecture

Smruti Ranjan Sarangi,
IIT Delhi

Chapter 8 Processor Design

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 These slides are meant to be used along with the book: Computer
Organisation and Architecture, Smruti Ranjan Sarangi, McGrawHill 2015
Visit: http://www.cse.iitd.ernet.in/~srsarangi/archbooksoft.html
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 Outline

Overview of a Processor
Detailed Design of each Stage
The Control Unit
Microprogrammed Processor
Microassembly Language
The Microcontrol Unit

3
 Processor Design

The aim of processor design

Implement the entire SimpleRisc ISA
Process the binary format of instructions
Provide as much of performance as possible
Basic Approach
Divide the processing into stages
Design each stage separately

4
 A Car Assembly Line

Similar to a car assembly line

Cast raw metal into the chassis of a car
Build the Engine
Assemble the engine and the chassis
Place the dashboard, and upholstery

5
 A Processor Divided Into Stages

Instruction Operand Execute Memory Register

Fetch Fetch Access Write
(IF) (OF) (EX) (MA) (RW)

Instruction Fetch (IF)

Fetch an instruction from the instruction memory

Compute the address of the next instruction

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 Operand Fetch (OF) Stage

Operand Fetch (OF)

Decode the instruction (break it into fields)

Fetch the register operands from the register file

Compute the branch target (PC + offset)

Compute the immediate (16 bits + 2 modifiers)

Generate control signals (we will see later)

7
 Execute (EX) Stage
The EX Stage
Contains an Arithmetic-Logical Unit (ALU)
This unit can perform all arithmetic
operations ( add, sub, mul, div, cmp, mod),
and logical operations (and, or, not)
Contains the branch unit for computing
the branch condition (beq, bgt)
Contains the flags register (updated by the
cmp instruction)
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 MA and RW Stages
MA (Memory Access) Stage
Interfaces with the memory system
Executes a load or a store
RW (Register Write) Stage
Writes to the register file
In the case of a call instruction, it writes the
return address to register, ra

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 Outline

Outline of a Processor
Detailed Design of each Stage
The Control Unit
Microprogrammed Processor
Microassembly Language
The Microcontrol Unit

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Instruction Fetch (IF) Stage
Fetch unit
isBranchTaken

32 branchPC
32 1

32 32 inst
pc

Instruction triggered by a negative

memory clock edge

1 1 - input 1
0 - input 0
0
Multiplexer
control signal

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 The Fetch unit
The pc register contains the program
counter (negative edge triggered)
We use the pc to access the instruction
memory
The multiplexer chooses between
pc + 4
branchTarget
It uses a control signal isBranchTaken
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 isBranchTaken
isBranchTaken is a control signal
It is generated by the EX unit
Conditions on isBranchTaken
Instruction Value of isBranchTaken
non-branch instruction 0
call 1
ret 1
b 1
branch taken 1
beq
branch not taken 0
branch taken 1
bgt
branch not taken 0

13
 Data Path and Control Path
The data path consists of all the elements in
a processor that are dedicated to storing,
retrieving, and processing data such as
register files, memory, and the ALU.

The control path primarily contains the

control unit, whose role is to generate the
appropriate signals to control the movement
of instructions, and data in the data path.

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 Control Path
Control path

Interconnection network

Data path elements

We will currently look at the hardwired control path.

15
 Operand Fetch Unit

Inst. Code Format Inst. Code Format

add 00000 add rd, rs1, (rs2/imm) lsl 01010 lsl rd, rs1, (rs2/imm)
sub 00001 sub rd, rs1, (rs2/imm) lsr 01011 lsr rd, rs1, (rs2/imm)
mul 00010 mul rd, rs1, (rs2/imm) asr 01100 asr rd, rs1, (rs2/imm)
div 00011 div rd, rs1, (rs2/imm) nop 01101 nop
mod 00100 mod rd, rs1, (rs2/imm) ld 01110 ld rd, imm[rs1]
cmp 00101 cmprs1, (rs2/imm) st 01111 st rd, imm[rs1]
and 00110 and rd, rs1, (rs2/imm) beq 10000 beq offset
or 00111 or rd, rs1, (rs2/imm) bgt 10001 bgt offset
not 01000 not rd, (rs2/imm) b 10010 b offset
mov 01001 mov rd, (rs2/imm) call 10011 call offset
ret 10100 ret

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 Instruction Formats

Format Definition
branch op (28-32) offset (1-27)
register op (28-32) I (27) rd (23-26) rs1 (19-22) rs2 (15-18)
immediate op (28-32) I (27) rd (23-26) rs1 (19-22) imm (1-18)
op opcode, offset branch offset, I immediate bit, rd destination register
rs1 source register 1, rs2 source register 2, imm immediate operand

Each format needs to be handled separately.

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 Register File Read
isRet

ra(15)
1
op1
A read port 1 D
rs1
inst[19:22]
0
inst rd
inst[23:26] 1 op2
A read port 2 D

rs2
inst[15:18]
0
Register
A
address
isSt
file D data

First input rs1 or ra(15) (ret instruction)

Second input rs2 or rd (store
instruction)
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 Register File Access
The register file has two read ports
1st Input
2nd Input
The two outputs are op1, and op2
op1 is the branch target (return address) in the
case of a ret instruction, or rs1
op2 is the value that needs to be stored in the
case of a store instruction, or rs2

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 Immediate and Branch Unit

imm 18 immx
calculate 32
inst[1:18]
immediate
pc
inst 27 shift by 2 bits 32 branchTarget
and extend sign

Compute immx (extended immediate),

branchTarget, irrespective of the instruction format.
For the branchTarget we need to choose between
the embedded target and op1 (ret)

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 OF Unit
Fetch unit Operand fetch unit Execute
(opcode, I bit) 6 Control unit
inst[27:32] unit

imm 18
calculate 32 immx
imm. operands

inst[1:18] immediate
pc

inst 27 shift by 2 bits 32 branchTarget

and extend sign

isRet
ra(15)
1
op1
rs1 A read port 1 D
reg. operands

0
inst[19:22]

rd op2
inst[23:26] 1 D
A read port 2
rs2 A address
inst[15:18] 0 Register
isSt file D data

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EX Stage Branch Unit
branchPC

branchTarget

from OF
0

op1
1
isRet

isBranchTaken

isUBranch
isBeq
flags.E
isBgt
flags.GT
flags

Generates the isBranchTaken Signal

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 ALU

op1 A
ALU
aluResult
B (Arithmetic
immx
1 logic unit)
op2
0 s

isImmediate aluSignals

Choose between immx and op2 based on the value of the I bit

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 Inside the ALU
isLsl isLsr isAsr

isAdd isSub isCmp

isLd A
isSt Shift
flags
A unit B

B
Adder
isOr isNot isAnd

isMul
A
A Logical
B Multiplier unit B

isDiv isMod
isMov

A
B
B Divider Mov
aluResult

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 Disabling some Inputs
We do not want all the units of the ALU to be
active at the same time because of we want to
save power
The instruction will only use 1 unit
Power is dissipated when the inputs or outputs
make a transition (0 1, 1 0)
We shall avoid a transition by not letting the new
inputs to propagate to units that do not require
them
They will thus have the old inputs (no switching)

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 Use a Transmission Gate
S

output = input (if S = 1)

Otherwise, the output is totally
disconnected from the input

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 EX Unit
Execute unit
branchPC
branchTarget

from OF
0
op1
1
isRet
isBranchTaken

isUBranch
isBeq
flags.E
isBgt
flags.GT
flags

op1 A
ALU
ALU and mem insts

aluResult
B (Arithmetic
immx
1 logic unit)
op2
0 s

isImmediate aluSignals

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 MA Unit

isLd isSt

32 op2
mdr
32 ldResult
Memory unit
32 aluResult
mar

mdr memory
data reg.
Data memory
mar memory
address reg.

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 RW Unit
register writeback unit
Register file
A
read port 1 isWb
D E ra(15)
1
write port A rd (inst[23:26])
A D 0
read port 2
D isCall

32 aluResult
00
32 ldResult result E enable
01
32
pc
10
A address
D data
isLd
4 isCall

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 1

pc + 4 0

pc Instruction
memory

Instruction Control
rd rs2 ra(15) rs1
unit
isRet
1 0 1 0
isSt
isWb
Register data
Immediate and
branch target file
reg
op2 op1
immx

01 1 0 isImmediate
isRet aluSignals

isBranchTaken
B A
Branch
ALU unit

mar mdr
isLd

Data memory Memory isSt

unit

pc

4 isLd
10 01 00 isCall

rd 0

ra(15) 1
data

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 Outline
Outline of a Processor
Detailed Design of each Stage
The Control Unit
Microprogrammed Processor
Microassembly Language
The Microcontrol Unit

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 The Ha rdwired Control Unit

opcode
inst[28:32]
Control control
I bit unit signals
inst[27]

Given the opcode and the immediate bit

It generates all the control signals

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 Control Signals

SerialNo. Signal Condition

1 isSt Instruction: st
2 isLd Instruction: ld
3 isBeq Instruction: beq
4 isBgt Instruction: bgt
5 isRet Instruction: ret
6 isImmediate I bit set to 1
7 isWb Instructions: add, sub, mul, div, mod,
and, or, not, mov, ld, lsl, lsr, asr, call
8 isUBranch Instructions: b, call, ret
9 isCall Instructions: call

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 Control Signals II
aluSignal
10 isAdd Instructions: add, ld, st
11 isSub Instruction: sub
12 isCmp Instruction: cmp
13 isMul Instruction: mul
14 isDiv Instruction: div
15 isMod Instruction: mod
16 isLsl Instruction: lsl
17 isLsr Instruction: lsr
18 isAsr Instruction: asr
19 isOr Instruction: or
20 isAnd Instruction: and
21 isNot Instruction: not
22 isMov Instruction: mov

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 Control signal Logic
opcode immediate bit
op5 op45 op3 op2 op1 I

Serial No. Signal Condition

1 isSt op5.op4.op3.op2.op1
2 isLd op5.op4.op3.op2.op1
3 isBeq op5.op4.op3.op2.op1
4 isBgt op5.op4.op3.op2.op1
5 isRet op5.op4.op3.op2.op1
6 isImmediate I
7 isWb ~(op5 + op5.op3.op1.(op4 + op2)) +
op5.op4.op3.op2.op1
8 isUbranch op5.op4.(op3.op2 + op3.op2.op1)
9 isCall op5.op4.op3.op2.op1

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 Control Signal Logic - II

aluSignals
10 isAdd op5.op4.op3.op2.op1 + op5.op4.op3.op2
11 isSub op5.op4.op3.op2.op1
12 isCmp op5.op4.op3.op2.op1
13 isMul op5.op4.op3.op2.op1
14 isDiv op5.op4.op3.op2.op1
15 isMod op5.op4.op3.op2.op1
16 isLsl op5.op4.op3.op2.op1
17 isLsr op5.op4.op3.op2.op1
18 isAsr op5.op4.op3.op2.op1
19 isOr op5.op4.op3.op2.op1
20 isAnd op5.op4.op3.op2.op1
21 isNot op5.op4.op3.op2.op1
22 isMov op5.op4.op3.op2.op1

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 Outline
Outline of a Processor
Detailed Design of each Stage
The Control Unit
Microprogrammed Processor
Microassembly Language
The Microcontrol Unit

37
 Microprogramming
Idea of microprogramming
Expose the elements in a processor to software
Implement instructions as dedicated software
routines
Why make the implementation of
instructions flexible ?
Dynamically change their behaviour
Fix bugs in implementations
Implement very complex instructions
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 Microprogrammed Data Path
Expose all the state elements to dedicated
system software firmware
Write dedicated routines in firmware for
implementing each instruction
Basic idea
1 SimpleRisc Instruction Several micro instructions
Execute each micro instruction
We require a microprogram counter, and
microinstruction memory
39
 Fetch Unit
pc Instruction memory ir

Shared bus
The pc is used to access the instruction memory.
The contents of the instruction are saved in the
instruction register (ir)

40
 Decode Unit
pc
ir
rs1 rs2 Immediate immx calc. branchTarget
I rd
unit offset

Shared bus

Divide the contents of ir into different

fields
I, rd, rs1, rs2, immx, and branchTarget

41
 The Register File
Shared bus

args
regVal regData regSrc

Register
file

regSrc (id of the source/dest register)

regData (data to be stored)
regVal (register value)
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 ALU
Shared bus

args
aluResult A B flags.E flags.GT

ALU flags

A, B ALU operands
args ALU operation type
aluResult ALU Result
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Memory Unit

Shared bus

args
ldResult mar mdr

Data
memory

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 Microprogrammed Data Path

opcode
control
unit pc Instruction memory ir
Immediate immx calc. branchTarget
I rd rs1 rs2
unit offset

Shared bus
args

args

args
ldResult mar mdr aluResult A B flags.E flags.GT regVal regData regSrc

Data Register
ALU flags
memory file

45
 Outline
Outline of a Processor
Detailed Design of each Stage
The Control Unit
Microprogrammed Processor
Microassembly Language
The Microcontrol Unit

46
 Internal Registers
SerialNo. Register Size Function
(bits)
1 pc 32 program counter
2 ir 32 instruction register
3 I 1 immediate bit in the instruction
4 rd 4 destination register id
5 rs 1 4 id of the first source register
6 rs 2 4 id of the second source register
7 immx 32 immediate embedded in the
instruction (after processing
modifiers)
8 branchTarget 32 branch target, computed as the
sum of the PC and the offset
embedded in the instruction
9 regSrc 4 contains the id of the register
that needs to be accessed in the
register file
10 regData 32 contains the data to be written
into the register file

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 Internal Registers - II

11 regVal 32 value read from the register file

12 A 32 first operand of the AlU
13 B 32 second operand of the ALU
14 flags.E 1 the equality flag
15 flags.GT 1 the greater than flag
16 aluResult 32 the ALU result
17 mar 32 memory address register
18 mdr 32 memory data register
19 ldResult 32 the value loaded from memory

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 Microinstructions

Basic Instructions
mloadIR Loads the instruction register (ir)
with the contents of the instruction.
mdecode Waits for 1 cycle. Meanwhile, all
the decode registers get populated
mswitch Loads the set of micro instructions
corresponding to a program instruction.

49
 Move Microinstructions

mmov r1, r2 : r1 r2
mmov r1, r2, <args> : r1 r2, send the
value of args on the bus
mmovi r1, <imm> : r1 imm

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Add and Branch Microinstructions

madd r1, imm, <args>

r1 r1 + imm
send <args> on the bus
mbeq r1, imm, <label>
if (r1 == imm), pc = addr(label)
mb <label>
pc = addr(label)

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Summary of Microinstructions

SerialNo. Microinstruction Semantics

1 mloadIR ir [pc]
2 mdecode populate all the decode registers
3 mswitch jump to the pc corresponding to
the opcode
4 mmov reg1, reg2, < args > reg1 reg2, send the value of
args to the unit that owns reg1,
< args > is optional
5 mmovi reg1, imm, < args > reg1 imm, < args > is optional

6 madd reg1, imm, < args > reg1 reg1+imm, < args > is
optional
7 mbeq reg1, imm, < label > if (reg1 = imm) pc addr(label)

8 mb <label> pc addr(label)

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Implementing Instructions in Microcode

The microcode preamble

.begin:
mloadIR
mdecode
madd pc, 4
mswitch

Load the program counter

Decode the instruction
Add 4 to the pc
Switch to the first microinstruction in the microcode
sequence of the prog. instruction
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3 Address Format ALU Instruction
/* transfer the first operand to the ALU */
mmov regSrc, rs1, <read>
mmov A, regVal

/* check the value of the immediate register */

mbeq I, 1, .imm
/* second operand is a register */
mmov regSrc, rs2, <read>
mmov B, regVal, <aluop>
mb .rw
/* second operand is an immediate */
.imm:
mmov B, immx, <aluop>

/* write the ALU result to the register file*/

.rw:
mmov regSrc, rd
mmov regData, aluResult, <write>
mb .begin

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 The mov Instruction
mov instruction

/* check the value of the immediate register */

mbeq I, 1, .imm
/* second operand is a register */
mmov regSrc, rs2, <read>
mmov regData, regVal
mb .rw
/* second operand is an immediate */
.imm:
mmov regData, immx

/* write to the register file*/

.rw:
mmov regSrc, rd, <write>

/* jump to the beginning */

mb .begin

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 The not Instruction
not instruction

/* check the value of the immediate register */

mbeq I, 1, .imm
/* second operand is a register */
mmov regSrc, rs2, <read>
mmov B, regVal, <not> /* ALU operation */
mb .rw
/* second operand is an immediate */
.imm:
mmov B, immx, <not> /* ALU operation */

/* write to the register file*/

.rw:
mmov regData, aluResult
mmov regSrc, rd, <write>

/* jump to the beginning */

mb .begin

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 The cmp Instruction
cmp instruction

/* transfer rs1 to register A */

mov regSrc, rs1, <read>
mov A, regVal

/* check the value of the immediate register

mbeq I, 1, .imm

/* second operand is a register */

mmov regSrc, rs2, <read>
mmov B, regVal, <cmp> /* ALU operation */
mb .begin

/* second operand is an immediate */

.imm:
mmov B, immx, <cmp> /* ALU operation */
mb .begin

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 The nop Instruction
mb .begin

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 The ld Instruction
ld instruction

/* transfer rs1 to register A */

mmov regSrc, rs1, <read>
mmov A, regVal

/* calculate the effective address */

mmov B, immx, <add> /* ALU operation */

/* perform the load */

mmov mar, aluResult, <load>

/* write the loaded value to the register file */

mmov regData, ldResult
mmov regSrc, rd, <write>

/* jump to the beginning */

mb .begin

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 The st Instruction
st instruction

/* transfer rs1 to register A */

mmov regSrc, rs1, <read>
mmov A, regVal

/* calculate the effective address */

mmov B, immx, <add> /* ALU operation */

/* perform the store */

mmov mar, aluResult
mmov regSrc, rd, <read>
mmov mdr, regVal, <store>

/* jump to the beginning */

mb .begin

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 beq and bgt Instructions

beq instruction bgt instruction

/* test the flags register /* test the flags register
mbeq flags.E, 1, .branch mbeq flags.GT, 1, .branch
mb .begin mb .begin

.branch: .branch:
mmov pc, branchTarget mmov pc, branchTarget
mb .begin mb .begin

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 call Instruction
call instruction

/* save PC + 4 in the return address register */

mmov regData, pc
mmovi regSrc, 15, <write>

/* branch to the function */

mmov pc, branchTarget
mb .begin

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 ret Instruction

ret instruction

/* save the contents of the return

address register in the PC */

mmovi regSrc, 15, <read>

mmov pc, regVal
mb .begin

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 Example
Change the call instruction to store the return address on the stack. The
preamble need not be shown.
Answer:

stack based call instruction

/* read the stack pointer */
mmovi regSrc, 14, <read>
madd regVal, -4 /* decrement the stack pointer */

/* set the memory address to the stack pointer */

mmov mar, regVal

/* update the stack pointer */

mmov regData, regVal, <write> /* update stack pointer */

/* write the return address to the stack */

mmov mdr, pc, <store>

/* jump to the beginning */

mb .begin

64
 Outline
Outline of a Processor

Detailed Design of each Stage

The Control Unit

Microprogrammed Processor

Microassembly Language

The Microcontrol Unit

65
 Shared Bus

Microcontrol unit

imm
isMBranch

pc
Decode unit pc
Read bus
Write bus
Reg. file, ALU, Mem unit
Reg. file, ALU, Mem unit

Shared bus

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Encoding an Instruction
Vertical Microprogramming (45 bit inst.)
3 bits type of instruction
5 bits source register
5 bits destination register
12 bits immediate
10 bit branch target in microcode memory
10 bit args value
3 bits (unit id)
7 bits operation code

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Horizontal Microprogramming

Encoding

10 bits branch target

12 bits immediate
10 bits args
33 bits bit vector of all the control signals

Total size of the encoded instruction : 65 bits

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Vertical Microprogramming

mux switch
branchTarget

opcode
1
Microprogram Decode Execute
pc unit unit
memory control
signals

Data path

Shared bus

69
Horizontal Microprogramming

opcode
switch
mux
isMBranch

M1 branchTarget
1
Microprogram Execute
pc memory unit
control
signals

Data path

Shared bus

70
THE END

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