Power and Energy Basics

Jan M. Rabaey

Low Power Design Essentials 2008 Chapter 3

 Chapter Outline

Metrics
Dynamic power
Static power
Energy-delay trade-offs

Low Power Design Essentials 2008 3.2

 Metrics

Delay (sec):
Performance metric
Energy (Joule)
Efficiency metric: effort to perform a task
Power (Watt)
Energy consumed per unit time
Power*Delay (Joule)
Mostly a technology parameter measures the efficiency of
performing an operation in a given technology
Energy*Delay = Power*Delay2 (Joule-sec)
Combined performance and energy metric figure of merit of
design style
Other Metrics: Energy-Delayn (Joule-secn)
Increased weight on performance over energy

Low Power Design Essentials 2008 3.3

 Where is Power Dissipated in CMOS?

Active (Dynamic) power

(Dis)charging capacitors
Short-circuit power
Both pull-up and pull-down on during transition
Static (leakage) power
Transistors are imperfect switches
Static currents
Biasing currents

Low Power Design Essentials 2008 3.4

 Active (or Dynamic) Power

Key property of active power:

Pdyn f
with f the switching frequency

Sources:
Charging and discharging capacitors
Temporary glitches (dynamic hazards)
Short-circuit currents

Low Power Design Essentials 2008 3.5

 Charging Capacitors
Applying a voltage step
1
E R CV 2
2
E01 CV 2 R
1
EC CV 2
2
V C

Value of R does not impact energy!

Low Power Design Essentials 2008 3.6

 Applied to Complementary CMOS Gate

2
Vdd E01 CLVDD

1 2
PMOS iL ER CLVDD
2
A1 NETWORK
Vout
AN CL EC
1 2
NMOS CLVDD
2
NETWORK

One half of the power from the supply is consumed in the

pull-up network and one half is stored on CL
Charge from CL is dumped during the 10 transition
Independent of resistance of charging/discharging network

Low Power Design Essentials 2008 3.7

 Circuits with Reduced Swing

0V

0V - VTH

V C

V VT

E 01 VC dV
dVC
dt CV C CV(V VTH )
0 dt 0

Energy consumed is proportional to output swing

Low Power Design Essentials 2008 3.8

 Charging Capacitors - Revisited
Driving from a constant current source
RC
ER ( )CV 2
T
R
E01 EC ER
1
EC CV 2
2
I C

CV
T
I

RC
E R I ( RI )dt RI 2T ( )CV 2
T
0

Energy dissipated in resistor can be reduced

by increasing charging time T (that is, decreasing I)
Low Power Design Essentials 2008 3.9
 Charging Capacitors

Using constant voltage or current driver?

Econstant_current < Econstant_voltage

if
T > 2RC

Energy dissipated using constant current charging

can be made arbitrarily small at the expense of delay:
Adiabatic charging

Note: tp(RC) = 0.69 RC

t090%(RC) = 2.3 RC

Low Power Design Essentials 2008 3.10

 Charging Capacitors

Driving using a sine wave (e.g. from resonant circuit)

R
1
EC CV 2
2
v(t) C

Energy dissipated in resistor can be made arbitrarily small

if frequency w << 1/RC
(output signal in phase with input sinusoid)

Low Power Design Essentials 2008 3.11

 Dynamic Power Consumption

Power = Energy/transition Transition rate

= CLVDD2 f01

= CLVDD2 f P01
= CswitchedVDD2 f

Power dissipation is data dependent depends

on the switching probability
Switched capacitance Cswitched = P01CL= a CL
(a is called the switching activity)

Low Power Design Essentials 2008 3.12

 Impact of Logic Function

Example: Static 2-input NOR gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 1 pB=1 = 1/2
0 1 0
Then transition probability
1 0 0 p01 = pOut=0 x pOut=1
1 1 0
= 3/4 x 1/4 = 3/16
If inputs switch every cycle
aNOR = 3/16
NAND gate yields similar result
Low Power Design Essentials 2008 3.13
 Impact of Logic Function

Example: Static 2-input XOR Gate

Assume signal probabilities

A B Out pA=1 = 1/2
0 0 0 pB=1 = 1/2
0 1 1
Then transition probability
1 0 1 p01 = pOut=0 x pOut=1
1 1 0
= 1/2 x 1/2 = 1/4
If inputs switch in every cycle
P01 = 1/4

Low Power Design Essentials 2008 3.14

 Transition Probabilities for Basic Gates

As a function of the input probabilities

p01
AND (1 - pApB)pApB
OR (1 - pA)(1 - pB)(1 - (1 - pA)(1 - pB))
XOR (1 - (pA +pB 2pApB))(pA + pB 2pApB)

Activity for static CMOS gates

a = p0p1

Low Power Design Essentials 2008 3.15

 Activity as a Function of Topology
XOR versus NAND/NOR

XOR

NAND/NOR

aNOR,NAND = (2N-1)/22N aXOR = 1/4

Low Power Design Essentials 2008 3.16

 How about Dynamic Logic?
VDD
Energy dissipated
when effective output is zero!
Precharge
or P01 = P0

Eval Always larger than P0P1!

E.g. P01(NAND) = 1/2N ; P01(NOR) = (2N-1)/2N

Activity in dynamic circuits hence always higher than static.

But capacitance most often smaller.

Low Power Design Essentials 2008 3.17

 Differential Logic?

VDD

Out Out Static:

Activity is doubled
Gate Dynamic:
Transition
probability is 1!

Hence: power always increases.

Low Power Design Essentials 2008 3.18

 Evaluating Power Dissipation of Complex Logic

Simple idea: start from inputs and propagate signal

probabilities to outputs
P1 0.1 0.045
0.5
0.9

0.1 0.99 0.989

0.1

0.5 0.25
0.5

But:
Reconvergent fanout
Feedback and temporal/spatial correlations

Low Power Design Essentials 2008 3.19

 Reconvergent Fanout (Spatial Correlation)
Inputs to gate can be interdependent (correlated)

reconvergence
A X A X
Z Z

no reconvergence reconvergent
PZ = 1-(1-PA)PB PZ = 1-(1-PA)PA ?
NO!
PZ: probability that Z=1 PZ = 1
Must use conditional probabilities
PZ = 1- PA . P(X|A) = 1
probability that X=1 given that A=1
Becomes complex and intractable real fast
Low Power Design Essentials 2008 3.20
 Temporal Correlations

Feedback Temporal correlation in

input streams
X
R Logic 01010101010101
00000001111111

Both streams have same P =

X is a function of itself 1 but different switching
correlated in time statistics

Activity estimation the hardest part of power analysis

Typically done through simulation with actual input
vectors (see later)

Low Power Design Essentials 2008 3.21

 Glitching in Static CMOS
Analysis so far did not include timing effects
A
X
B Z
C

ABC 101 000

Z
Glitch

Gate Delay

Also known as dynamic hazards:

The result is correct, A single input change causing
but extra power is dissipated multiple changes in the output

Low Power Design Essentials 2008 3.22

 Example: Chain of NAND Gates

Out1 Out2 Out3 Out4 Out5

1

3.0
Out6
Out2
2.0
Voltage (V)

Out6
Out8

1.0 Out7
Out1
Out5
Out3
0.0
0 200 400 600
Time (ps)

Low Power Design Essentials 2008 3.23

 What Causes Glitches?
A
A
X B
B X
Z
Y Y
C
C
Z
D D

A,B A,B

C,D C,D

X X

Y Y

Z Z

Uneven arrival times of input signals of gate due to

unbalanced delay paths
Solution: balancing delay paths!
Low Power Design Essentials 2008 3.24
 Short-Circuit Currents

(also called crowbar currents)

V DD
V DD -V T

vin
VT
V in I sc V out
I peak t
CL ishort

PMOS and NMOS simultaneously on during transition

Psc ~ f

Low Power Design Essentials 2008 3.25

 Short-Circuit Currents
VDD
VDD

Isc IMAX
Isc ~ 0

Vout Vout
Vin
Vin CL
CL

x 104
2.5

Large load 2 CL = 20 fF Small load

1.5
CL = 100 fF
1
CL = 500 fF
0.5

0.5
0 20 40 60
time (s)
Equalizing rise/fall times of input and output signals limits Psc to 10-15%
of the dynamic dissipation
Low Power Design Essentials 2008 [Ref: H. Veendrick, JSSC84] 3.26
 Modeling Short-Circuit Power

Can be modeled as capacitor

in
C SC k (a b)
out
a, b: technology parameters
k: function of supply and threshold voltages, and transistor sizes

ESC CSCVDD 2

Easily included in timing and power models

Low Power Design Essentials 2008 3.27

 Transistors Leak

Drain leakage
Diffusion currents
Drain-induced barrier lowering (DIBL)
Junction leakages
Gate-induced drain leakage (GIDL)
Gate leakage
Tunneling currents through thin oxide

Low Power Design Essentials 2008 3.28

 Sub-threshold Leakage

Off-current increases exponentially when reducing VTH

VTH
W
I leak I0 10 S
Pleak = VDD.Ileak
W0
Low Power Design Essentials 2008 3.29
 Sub-Threshold Leakage

Leakage current increases with drain voltage

(mostly due to DIBL)
VTH d VDS
W
I leak I0 10 S (for VDS > 3 kT/q)
W0
Hence
VTH d VDD
W
Pleak (I 0 10 S )(VDD10 S )
W0

Leakage Power strong function of supply voltage

Low Power Design Essentials 2008 3.30

 Stack Effect

Assume that body effect in short

channel transistor is small
NAND gate: VM VTH d (VDD VM )
I leak, M 1 I 0 10 S
VDD
VTH d VM
I leak, M 2 I 0 10 S

d
VM VDD
1 2d
d VDD 1 d
I stack ( )
1 2 d (instead of the
10 S
expected factor of 2)
I inv

Low Power Design Essentials 2008 3.31

 Stack Effect
-9
x 10
3

2.5
90 nm NMOS

IM1
Ileak (A)

factor 9
1.5 IM2
1

0.5
Leakage Reduction
0
2 NMOS 9
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
3 NMOS 17
VM (V)
4 NMOS 24
2 PMOS 8
3 PMOS 12
4 PMOS 16

Low Power Design Essentials 2008 3.32

 Gate Tunneling
V DD
Exponential function of supply voltage
IGD~ e-ToxeVGD, IGS~ e-ToxeVGS I SUB

Independent of the sub-threshold

V DD 0V
leakage
-10
I GD
x 10

1.8
I Leak
1.6
90 nm CMOS
1.4 I GS
1.2
Igate (A)

0.8
Modeled in BSIM4
Also in BSIM3v3 (but not
0.6
always included in foundry
0.4 models)
0.2 NMOS gate leakage usually
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
worse than PMOS
Low Power Design Essentials 2008 VDD (V) 3.33
 Other sources of static power dissipation

Diode (drain-substrate) reverse bias currents

p+ n+ n+ p+ p+ n+
n well

p substrate

Electron-hole pair generation in depletion region of reverse-

biased diodes
Diffusion of minority carriers through junction
For sub-50nm technologies with highly-doped pn junctions,
tunneling through narrow depletion region becomes an issue
Strong function of temperature
Much smaller than other leakage components in general
Low Power Design Essentials 2008 3.34
 Other sources of static power dissipation

Circuit with dc bias currents:

sense amplifiers,
voltage converters
and regulators,
sensors, mixed-signal
components, etc

Should be turned off if not used, or standby current should

be minimized

Low Power Design Essentials 2008 3.35

 Summary of Power Dissipation Sources

P ~ a CL CCS Vswing VDD f I DC I Leak VDD

a switching activity
CL load capacitance IDC static current
CCS short-circuit Ileak leakage current
capacitance
Vswing voltage swing
f frequency

energy
P rate static power
operation

Low Power Design Essentials 2008 3.36

 The Traditional Design Philosophy

Maximum performance is primary goal

Minimum delay at circuit level
Architecture implements the required function
with target throughput, latency
Performance achieved through optimum sizing,
logic mapping, architectural transformations.
Supplies, thresholds set to achieve maximum
performance, subject to reliability constraints

Low Power Design Essentials 2008 3.37

 CMOS Performance Optimization

Sizing: Optimal performance with equal fanout per stage

CL

Extendable to general logic cone through logical effort

Equal effective fanouts (giCi+1/Ci) per stage
Example: memory decoder
predecoder word driver

3 15 word
addr
input line
CW CL

Low Power Design Essentials 2008 [Ref: I. Sutherland, Morgan-Kaufman98] 3.38

 Model not Appropriate Any Longer
Traditional scaling model
1
If VDD 0 . 7 , and Freq ( ),
0 .7
1 1
Power CVDD
2
f ( 1 . 14 2 ) ( 0 . 7 2 ) ( ) 1 .3
0 .7 0 .7

Maintaining the frequency scaling model

If VDD 0 . 7 , and Freq 2 ,
1
Power CVDD 2
f ( 1 . 14 2 ) ( 0 . 7 2 ) ( 2 ) 1 . 8
0 .7

While slowing down voltage scaling

If VDD 0 . 85 , and Freq 2 ,
1
Power CVDD 2
f ( 1 . 14 2 ) ( 0 . 85 2 ) ( 2 ) 2 . 7
0 .7

Low Power Design Essentials 2008 3.39

 The New Design Philosophy

Maximum performance (in terms of

propagation delay) is too power-hungry,
and/or not even practically achievable
Many (if not most) applications either can
tolerate larger latency, or can live with lower
than maximum clock-speeds
Excess performance (as offered by
technology) to be used for energy/power
reduction
Trading off speed for power
Low Power Design Essentials 2008 3.40
 Relationship Between Power and Delay

-4 -10
x 10 x 10
1 5
0.8 4
Power (W)

Delay (s)
0.6 3
A
0.4 2
0.2 1
B
0 04
4 A
3 3 B
0 -0. 4 -0.4
2 2 0
1 0.8 0.4 1 0.8 0.4

For a given activity level, power is reduced while delay is unchanged if

both VDD and VTH are lowered such as from A to B.

Low Power Design Essentials 2008 [Ref: T. Sakurai and T. Kuroda, numerous references] 3.41
 The Energy-Delay Space

Equal performance curves

VDD

Equal
energy
curves

VTH
Energy minimum
Low Power Design Essentials 2008 3.42
 Energy-Delay Product as a Metric

3.5

3
delay 90 nm technology
2.5 VTH approx 0.35V

1.5

1 energy-delay
0.5 energy

0
0.6 0.7 0.8 0.9 1 1.1 1.2
VDD

Energy-delay exhibits minimum at approximately 2 VTH

(typical unless leakage dominates)

Low Power Design Essentials 2008 3.43

 Exploring the Energy-Delay Space
Energy
Unoptimized
design

Emax Pareto-optimal
designs

Emin
Dmin Dmax Delay

In energy-constrained world, design is trade-off process

Minimize energy for a given performance requirement
Maximize performance for given energy budget

Low Power Design Essentials 2008 [Ref: D. Markovic, JSSC04] 3.44

 Summary

Power and energy are now primary design

constraints
Active power still dominating for most
applications
Supply voltage, activity and capacitance the key
parameters
Leakage becomes major factor in sub-100nm
technology nodes
Mostly impacted by supply and threshold voltages
Design has become energy-delay trade-off
exercise!

Low Power Design Essentials 2008 3.45

 References

D. Markovic, V. Stojanovic, B. Nikolic, M.A. Horowitz, R.W.

Brodersen, Methods for True Energy-Performance Optimization,
IEEE Journal of Solid-State Circuits, vol. 39, no. 8, pp. 1282-1293,
Aug. 2004.
J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits:
A Design Perspective, 2nd ed, Prentice Hall 2003.
Takayasu Sakurai, Perspectives on power-aware
electronics, Digest of Technical Papers ISSCC, pp. 26-29, Febr.
03.
I. Sutherland, B. Sproull, and D. Harris, Logical Effort, Morgan
Kaufmann, 1999.
H. Veendrick, Short-Circuit Dissipation of Static CMOS Circuitry
and its Impact on the Design of Buffer Circuits, IEEE Journal of
Solid-State Circuits, Vol. SC-19, no. 4, pp.468473, 1984.

Low Power Design Essentials 2008 3.46