MEMORY SUBSYSTEMS

Types of memory
Memory connections ( pin
assignments )
Memory Devices
Memory capacity and organizations
Address decoding
 Primary and Secondary Memory
Computer memory is divided into primary memory and secondary memory.
Primary memory
fast
random access memory (RAM), read-only memory (ROM), Cache
RAM holds the programs and data that the processor is actively
working with.
ROM contains software that is used in Input/Output operations. It
also contains software that loads the Operating System in Primary
Memory.
The CPU can read and write to RAM but it can only read from ROM.
RAM is volatile while ROM is not.
Secondary memory is used for long-term storage of programs and data.
Examples of secondary memory devices are:
hard disks, floppy disks and CD ROMs.
Memory Hierarchy : organization of different memory level in computers
Primary and Secondary Memory Comparison

Primary memory Secondary memory

Fast Slow
Expensive Cheap
Low capacity Large capacity
Connects directly to the Not connected directly to
processor the processor
Memory Hierarchy
 Memory Types
RAM (Random access memory):
SRAM (Static RAM) (flip-flop gates)
DRAM (Dynamic RAM)

ROM (Read only memory)

PROM (programmable)
EPROM (erasable programmable)
EEPROM (electronically erasable programmable), flash
memory

Generally, all memory devices have :

address inputs and outputs, or just outputs
a pin for selection
one or more pins that control the operation of the memory
 Address Decoding

To attach a memory device to the microprocessor

To select particular set of addresses i.e. 00000 0FEEE
to decode the address from the microprocessor to make the memory
function at a unique section or partition of the memory map.

Why Decode Memory?

To corrects the mismatch between microprocessor and memory
component (because of a difference in the number of address
connections surfaces)

Commonly found address decoders include :

the 3-to-8 Line Decoder (74LS138)
the 74LS139 2-to-4 line decoder
Simple logic gate
Programmable Device : CPLD complex programmable logic devices
 Address decoding using simple NAND gate

Using partial memory addressing space

Addr[19:0]
FFFFF

Highest address 0011 0 111 1111 1111 1111

37FFF
32KB Lowest address 0011 0 000 0000 0000 0000
30000
These 5 address lines These 15 address lines select
00000 are not changed. They one of the 215 (32768) locations
set the base address inside the RAMs

Addr[14:0]
32KB
Addr[19] CS
Addr[18]
Addr[17]
Addr[16]
Addr[15] Can we design a decoder such that the first address
IO/M of the 32KB memory is 37124H?
Using a decoder to connect to RAM
 Address decoding using simple NAND gate and an
address decoder
Using partial memory addressing space
Addr[19:0]
FFFFF

Highest address 0011 0 111 1111 1111 1111

37FFF
32KB Lowest address 0011 0 000 0000 0000 0000
30000
These 5 address lines These 15 address lines select
00000 are not changed. They one of the 215 (32768) locations
set the base address inside the RAMs
 Addr[14:0]
32KB

Addr[19]
CS
Addr[18]
Addr[17]
Addr[16]
Addr[15]

IO/M
 Memory Address Decoding (1)

Design a 1MB memory system consisting of multiple memory chips

Solution 1:

256KB 256KB 256KB 256KB

CS CS CS CS

Addr[17:0]
Addr[18]
2-to-4
Addr[19] decoder
CS
IO/M
 Memory Address Decoding (2)

Design a 1MB memory system consisting of multiple memory chips

Solution 2:

256KB 256KB 256KB 256KB

CS CS CS CS

Addr[19:2]

Addr[1]
2-to-4
decoder
Addr[0]
CS
IO/M
 Memory Address Decoding (3)

Design a 1MB memory system consisting of multiple memory chips

Solution 3:

256KB 256KB 256KB 256KB

Addr[19:18] CS CS CS CS
Addr[16:7]
Addr[5:0]

Addr[17]
2-to-4
decoder
Addr[6]
CS
IO/M It is a bad design, but still works!
Does it work if the last memory chip is removed?
 Memory Address Decoding (4)

Design a 1MB memory system consisting of multiple memory chips

Solution 4:

256KB 256KB 512KB

CS CS CS

Addr[17:0]

Addr[18] Addr[18]
Addr[19]
IO/M Addr[19]
Addr[18]
Addr[19]
IO/M IO/M
Memory Address and Memory content
Memory Devices
 General descriptions of a Memory Chip
Address Connections
are used to select one of the memory location within the device
Data Connections
are used to enter information to be stored in a memory location
and also to retrieve information read from a memory location.
Manufacturers list their memory as, for example, 4K x 4, which
means that the device has 4K memory locations (4096) and 4-
bits are stored in each location.
Selection Connections
Memory selection is accomplished via a chip selection pin (CS)
on many RAMs or a chip enable pin (CE) on many EPROM or
ROM memories ( see example in next slaids )
Control Connections
Memory function is selected by an output enable pin (OE), for
reading data.
For writing data, memory function is selected by the write enable
pin (WE).
 Memory Devices
1. ROM Memory
ROM permanently stores programs and data that are resident
to the system and must not change when power is disconnected.
This type of memory is often called nonvolatile memory, for
example :
EPROM (erasable programmable read-only memory) is
programmed by an EPROM programmer and can be erased if
exposed to ultraviolet light.
The flash memory (EEPROM) is programmed in the system
( in circuit ) by using a 12V programming pulse
Each location can be written only 10,000 times.
Programming of EEPROM takes more time than reading
so it can not substitute RWM
2. RAM : Read Access Memory, Read Write Memory
Static RAM (SRAM) Devices
retains data for as long as the system power system is
attached.
these memory types are available in sizes up to 128K
x8
stores temporary data and is used when the size of
the read/write memory is relatively small
Dynamic RAM (DRAM) Memory
the size is up to 16M x 1
DRAM = SRAM, except that it retains data for only
2 or 4 ms on an integrated capasitor (see Fig. 9-7)
Another disanvantage of DRAM memory is that it
requires so many address pins that the manufacturers
have multiplexed the address inputs
 A memory unit

n data input lines

k address lines
Memory unit
Read 2k words
Write n bit per word

n data output lines

 Memory Connections: diagram

KxN
Address[log2(K)-1:0]

M Data[N-1:0]
CS
E
OE M
WE

Chip Select must be asserted before Memory will respond

to read or write operation. If negated, data bus is
high impedance.
OE Asserted for read operation, Memory will drive data
lines.
WE Asserted for a write operation (Memory inputs data
from data pins).
 Memory Capacity and Memory Organization
KxN
Address[(log2(K)-1):0] M Data[(N-1):0]
E
M
K locations, N bits per location , Address bus has log2(K) address lines,
data bus has N data lines.
Chip capacity : number of bits a memory chipc can store , defined in bits ,
i.e. 1 Kbits, Mbits, ( note : storage capacities of computer : Bytes)
memory chip has 64M : bits <-> Computer has 64M : bytes
Memory organization :
Each location can hold 1, 4 or 8 bits ( designed internally ) ; How many
location : address pins.
referred as organization ; x is the number of address pins , y is number of
data pins in each location
 Semiconductor Memory Device Architecture

nm Device
log2n inputs called address lines
m outputs called data lines

Storage Cell Array

A1 24
Decoder
A0

4 x 5 Memory Buffers
(4 locations, 5 bits per
D4 D3 D 2 D1 D0
location).
Examples:
Ex 1. MC has 12 address pin and 8 data pin, (a) organization ( b)
capacity x 2x
Ex.2 A 512K MC has 8 pins for data (a) the organization (b)
number of address pins 10 1K
Ex 3. Organization ? Capacity ? Of the following EPROM ? 11 2K
12 4K
13 8K
14 16K
15 32K
16 64K
17 128K
18 256K
19 512K
20 1M
21 2M
22 4M
Ex.4 Intel 2716 has organization : 2K X 8. What is its capacity, 23 8M
how many address lines it has
Block Diagram of ROM and RAM
 Expanding Byte Length, Word Capacity
Byte Length Capacity
Increases the storage
length
Example 8086 ( 16 bit data
bus ) to 27c256 EPROMS
which 32K X 8
Address inputs, Chip
Enable, and output Enable
lines are connected in
parallel
Total capacity :
32K X 16
or
512KB
 8 bit is expanded to 16 bit ( 8086)
4 bit expansion to 8 bit
Design Example 1 : 16K X 16 bit memory using 8K X 8 chip ( SRAM )
Design Example 2:

SRAM EPROM
14 14
A0-A13 A0-A13

4363 27128
4
I/O0-I/O4 8
OE O0-O7
WE

OE
CE
CE
0000016
. SRAM 1
. SRAM 2
.
03FFF16
32KByte SRAM
0400016
. SRAM 3
. SRAM 4
.
07FFF16

F800016
.
EPROM 1
.
.
FBFFF16
32KByte EPROM
FC00016
.
. EPROM 2
.
FFFFF16
 A19A18A17A16 A15A14A13A12 A11A10A9A8 A7A6A5A4 A3A2A1A0

SRAM 1 0000016 0000 0000 0000 0000 0000

SRAM 2
03FFF16 0000 0011 1111 1111 1111
SRAM 3
0400016 0000 0100 0000 0000 0000
SRAM 4 07FFF16 0000 0111 1111 1111 1111

F800016 1111 1000 0000 0000 0000

EPROM 1
FBFFF16 1111 1011 1111 1111 1111
FC00016 1111 1100 0000 0000 0000
EPROM 2
FFFFF16 1111 1111 1111 1111 1111
 A14
One decoder for SRAM A15
A16

A17
A18
A19

One decoder for EPROM A14

A15
A16

A17
A18
A19