Advanced

Microprocessors and
Peripherals
Sarju S
Lecturer
Department of Computer Science and Engineering
SJCET, Palai
Module V
Additional features of 80386 – Paging


mechanism – Interfacing coprocessors

in 80386 – Additional features of
Pentium Processors. Brief study of
latest processors of Intel & AMD
(Architecture not required) –
Introduction to RISC processors

80386
32-bit microprocessor
Physical memory space is 4Gbytes(232 )
Virtual memory space is 64 terabytes.
The memory management section of 80386
supports
 Virtual memory
 Paging
 Four levels of protection
Operates in two mode
 Real address mode
 Protected mode
The concept of paging is introduced in 80386

Real Address mode of
80386
Works as s fast 8086 with 32-bit registers and
data types.
The addressing techniques, memory size,
interrupt handling in this mode of 80386 is
similar to real addressing mode of 80286.

Memory addressing in Real
Mode
In this 80386 can address at the most 1Mbytes
of physical memory using the lines A0-A19.
Paging unit is disabled in real address mode.
Physical address formation is similar to 8086
and 80286
Protected mode of 80386
In this mode it can address 4Gigabytes of physical
memory and 64 terabytes of virtual memory.
Addressing in protected mode
 The contents of the segment registers are used as
selectors to address descriptors which contain
the segment limit, base address and access right
bytes of the segment.
 The effective address(offset) is added with
segment base address to calculate the linear
address.
 This linear address is further used as physical
address, if the paging unit is disabled, otherwise,
the paging unit converts the linear address into
physical address.
 Physical Address

SEGMEN OFFSET 4 K Byes

T
4 K Byes

4 K Byes

4 K Byes

ACCESS 386 CPU Physica

4 K Byes

RIGHTS
LIMIT PAGING l
MEMORY
Address 4 K Byes
BASE + MECHANIS OPERAND
ADDRESS M 4 K Byes
Segment Page
Descriptor Frame
Address 4 K Byes
Linear
Address Physical Pag

Fig: Paging Unit Enabled in Protected Mode

Addressing
Segmentation
DESCRIPTOR TABLES: These descriptor
tables and
 registers are manipulated by the operating
system to ensure the correct operation of the
processor, and hence the correct execution of
the program.


Three types of the 80386 descriptor tables are

Global Descriptor Tale(GDT)
Local descriptor Table(LDT)
Interrupt Descriptor Table(IDT)
 Segmentation(cont….)
DESCRIPTORS: The 80386 descriptors have a
20-bit segment limit and 32-bit segment
address.

Segment Base 15….0 Segment Base 15….0
 G D
Base 0 AVLLimit P DPL S Type A Base
31…
 19… 23…
24 16 26
Fig: Structure of a Segment Descriptor
Segmentation(cont….)
Descriptor Attribute Bits: The A (accessed)
attributed bit indicates whether the segment
has been accessed by the CPU or not.

The TYPE field decides the descriptor type and
hence the segment type.

The S bit decides whether it is a system
descriptor (S=0) or code/data segment
descriptor ( S=1).
Segmentation(cont….)
 The DPL field specifies the descriptor privilege level.

 The D bit specifies the code segment operation size. If D=1,
the segment is a 32-bit operand segment, else, it is a 16-bit
operand segment.

 The P bit (present) signifies whether the segment is present
in the physical memory or not. If P=1, the segment is
present in the physical memory.

 The G (granularity) bit indicates whether the segment is page
addressable.


 The zero bit must remain zero for compatibility with future
process.
Segmentation(cont….)
The AVL (available) field specifies whether the
descriptor is for user or for operating system.

The 80386 has five types of descriptors listed as
follows:
 1. Code or Data Segment Descriptors.
 2. System Descriptors.
 3. Local descriptors.
 4. TSS (Task State Segment) Descriptors.
 5. GATE Descriptors.


The 80386 provides a four level protection

mechanism exactly in the same way as the
80286 does.
Paging
PAGING OPERATION: Paging is one of the memory
management techniques used for virtual memory
multitasking operating system.

The segmentation scheme may divide the physical
memory into a variable size segments but the paging
divides the memory into a fixed size pages.

The segments are supposed to be the logical segments
of the program, but the pages do not have any logical
relation with the program.

The pages are just fixed size portions of the program
module or data.
Paging (cont..)
The advantage of paging scheme is that the complete
segment of a task need not be in the physical memory
at any time.

Only a few pages of the segments, which are required
currently for the execution need to be available in the
physical memory. Thus the memory requirement of
the task is substantially reduced, relinquishing the
available memory for other tasks.

Whenever the other pages of task are required for
execution, they may be fetched from the secondary
storage.

The previous page which are executed, need not be
available in the memory, and hence the space
Paging (cont..)
Thus paging mechanism provides an effective technique
to manage the physical memory for multitasking
systems.

Paging Unit: The paging unit of 80386 uses a two level
table mechanism to convert a linear address provided
by segmentation unit into physical addresses.

The paging unit converts the complete map of a task
into pages, each of size 4K. The task is further
handled in terms of its page, rather than segments.

The paging unit handles every task in terms of three
components namely page directory, page tables and
page itself.
Paging (cont..)
Paging Descriptor Base Register: The control
register CR2 is used to store the 32-bit linear
address at which the previous page fault was
detected.

The CR3 is used as page directory physical base
address register, to store the physical starting
address of the page directory.

The lower 12 bit of the CR3 are always zero to
ensure the page size aligned directory. A move
operation to CR3 automatically loads the page
table entry caches and a task switch operation, to
load CR0 suitably.
Paging (cont..)
Page Directory : This is at the most 4Kbytes in
size. Each directory entry is of 4 bytes, thus a
total of 1024 entries are allowed in a directory.

The upper 10 bits of the linear address are used as
an index to the corresponding page directory
entry. The page directory entries point to page
tables.

Page Tables: Each page table is of 4Kbytes in size
and many contain a maximum of 1024 entries.
The page table entries contain the starting
address of the page and the statistical
information about the page.
Paging (cont..)
 The upper 20 bit page frame address is combined with the
lower 12 bit of the linear address. The address bits A12-
A21 are used to select the 1024 page table entries. The
page table can be shared between the tasks.

 The P bit of the above entries indicate, if the entry can be
used in address translation.

 If P=1, the entry can be used in address translation,
otherwise it cannot be used.

 The P bit of the currently executed page is always high.

 The accessed bit A is set by 80386 before any access to the
page. If A=1, the page is accessed, else not accessed.
Paging (cont..)
 The D bit ( Dirty bit) is set before a write operation to the
page is carried out. The D-bit is undefined for page director
entries.

 The OS reserved bits are defined by the operating system
software.

 The User / Supervisor (U/S) bit and read/write bit are used to
provide protection. These bits are decoded to provide
protection under the 4 level protection model.

 The level 0 is supposed to have the highest privilege, while
the level 3 is supposed to have the least privilege.

 This protection provide by the paging unit is transparent to
the segmentation unit.
Virtual 8086 Mode
In its protected mode of operation, 80386DX provides a
virtual 8086 operating environment to execute the
8086 programs.

The real mode can also used to execute the 8086
programs along with the capabilities of 80386, like
protection and a few additional instructions.
Once the 80386 enters the protected mode from the
real mode, it cannot return back to the real mode
without a reset operation.

Thus, the virtual 8086 mode of operation of 80386,
offers an advantage of executing 8086 programs while
in protected mode.
Virtual 8086 Mode
(cont..)
 The address forming mechanism in virtual 8086 mode is
exactly identical with that of 8086 real mode.

 In virtual mode, 8086 can address 1Mbytes of physical
memory that may be anywhere in the 4Gbytes address
space of the protected mode of 80386.

 Like 80386 real mode, the addresses in virtual 8086 mode lie
within 1Mbytes of memory.

 In virtual mode, the paging mechanism and protection
capabilities are available at the service of the
programmers.

 The 80386 supports multiprogramming, hence more than one
programmer may be use the CPU at a time.
Virtual 8086 Mode
(cont..)
Paging unit may not be necessarily enable in virtual
mode, but may be needed to run the 8086 programs
which require more than 1Mbyts of memory for
memory management function.

In virtual mode, the paging unit allows only 256 pages,
each of 4Kbytes size.

Each of the pages may be located anywhere in the
maximum 4Gbytes physical memory. The virtual mode
allows the multiprogramming of 8086 applications.

The virtual 8086 mode executes all the programs at
privilege level 3.Any of the other programmes may
deny access to the virtual mode programs or data.
Virtual 8086 Mode
(cont..)
 However, the real mode programs are executed at the
highest privilege level, i.e. level 0.

 The virtual mode may be entered using an IRET instruction at
CPL=0 or a task switch at any CPL, executing any task
whose TSS is having a flag image with VM flag set to 1.

 The IRET instruction may be used to set the VM flag and
consequently enter the virtual mode.

 The PUSHF and POPF instructions are unable to read or set
 the VM bit, as they do not access it.

 Even in the virtual mode, all the interrupts and exceptions are
handled by the protected mode interrupt handler.
Virtual 8086 Mode
(cont..)
To return to the protected mode from the
virtual mode, any interrupt or execution may
be used.

As a part of interrupt service routine, the VM
bit may be reset to zero to pull back the
80386 into protected mode.
Segment Base 15….0 Segment Base 15….0
Base G D 0 AVLLimit P DPL S Type A Base
31… 19… 23…
24 16 26
Base Base address of the segment
Limit Length of the segment
P Present bit – 1=Present, 0=Not present
DPL Descriptor privilege level 0-3
S Segment Descriptor – 0= System Descriptor 1=Code/Data segment
descriptor
Type Type of segment
A Access bit
G Granularity bit – 1=Segment length is page granular
SELECT OFFSET
OR
+ MEMORY

UPTO 4GB MEMORY

OPERAND
ACCESS
RIGHTS
LIMIT
BASE
SEGMENT BASE
ADDRESS
SEGMENT DESCRIPTOR ADDRESS

Fig: Protected Mode Addressing without Paging Unit