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3851.lecture1 and 2

The 8086 microprocessor is divided into two units: the bus interface unit (BIU) and the execution unit (EU). The BIU handles data and address transfers between the EU and memory/ports. It contains four segment registers - CS, SS, ES, DS - that point to different memory segments, and the instruction pointer register that holds the offset of the next instruction. The BIU also has a queue that allows pipelining of instruction fetching and execution.

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91 views

3851.lecture1 and 2

The 8086 microprocessor is divided into two units: the bus interface unit (BIU) and the execution unit (EU). The BIU handles data and address transfers between the EU and memory/ports. It contains four segment registers - CS, SS, ES, DS - that point to different memory segments, and the instruction pointer register that holds the offset of the next instruction. The BIU also has a queue that allows pipelining of instruction fetching and execution.

Uploaded by

Aditya Gautam
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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8086 MICROPROCESSOR

RAM MURAT SINGH


MICROPROCESSOR 8086
• The 8086 was the first 16-bit microprocessor introduced by Intel in 1978.
• It is implemented in HMOS ( High density short channel MOS) technology.
• It is packaged in a 40-pin CERDIP or plastic package.
• It is available in three clock rates:
8086 in 5Mhz,
8086-2 in 8Mhz, and
8086-1 in 10Mhz.
• 8086 operates in both single processor and multiple processor
configuration to achieve high performance levels.
• It has 20-address bus and hence can access as much as 1MB(220) memory
locations.
• It has 16-bit data bus.
8086 INTERNAL BLOCK DIAGRAM
FUNCTIONAL BLOCK DIAGRAM OF 8086

8086 Microprocessor is divided into two


independent functional parts.
• Bus interface unit (BIU).
• Execution unit (EU).
BUS INTERFACE UNIT
• The bus interface unit handles all transfer of
data and addresses on the buses for the
Execution unit.
• This unit sends out addresses, fetches
instructions from memory, reads data from
ports and memory and writes data to ports
and memory.
DIFFERENT PARTS OF BIU
• SEGMENT REGISTERS
• INSTRUCTION POINTER
• THE QUEUE
SEGMENT REGISTERS
BIU contains four 16-bit segment registers as
follows:
• Code segment (CS) register.
• Stack segment (SS) register.
• Extra segment (ES) register.
• Data segment (DS) register.
FUNCTION OF SEGMENT REGISTERS
• In 8086 complete 1MB memory is divided into 16 logical segments.
• Each segment thus contains 64 KB of memory.
• While addressing any location in the memory bank, the Physical address is
calculated from two parts, the first part is Segment address, and the
second is Offset.

• The segment registers contain 16-bit segment base addresses related to


different segments.
• Thus the CS, DS, ES, SS segment registers, respectively contain the
segment addresses for the Code, Data, Extra and Stack segments.
• They may or may not be physical separated.
• Each segment register contains a 16-bit base address that points to the
lowest-addressed byte of that particular segment in memory.
GENERATION OF PHYSICAL ADDRESS

Segment address- 1005H


Offset address - 5555H
Segment address-1005H- 0001 0000 0000 0101
Shifted by 4-bit positions-0001 0000 0000 0101 0000
+
Offset address - 0101 0101 0101 0101
Physical address -0001 0101 0101 1010 0101
1 5 5 A 5
INSTRUCTION POINTER
• It is 16-bit register , which identifies the location
of the next word of instruction code that is to be
fetched in the current code segment.
• IP contains an offset instead of the actual address
of the next instruction.
• The 20-bit address produced after addition of the
offset stored in IP to segment base address in the
CS is called the Physical address of the code byte.
THE QUEUE
• The last section of BIU is the FIFO group of
registers called a queue. It is basically a group of
registers.
• This arrangement makes possible for the BIU to
fetch the instruction byte while EU is decoding
an instruction or executing an instruction which
does not require use of buses.
• This arrangement is called pipelining.
• This is done to speed up the program execution.

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