Overview of

Microprocessors
Lecturer: Sri Parameswaran
Notes by : Annie Guo

Week3 1
Lecture overview
 Introduction to microprocessors
 Instruction set architecture
 Typical commercial microprocessors

Week3 2
Microprocessors
 A microprocessor is a CPU on a single chip.
 If a microprocessor, its associated support
circuitry, memory and peripheral I/O
components are implemented on a single
chip, it is a microcontroller.
 We use AVR microcontroller as the example in
our course study

Week3 3
Microprocessor types
 Microprocessors can be characterized based
on
 the word size
 8 bit, 16 bit, 32 bit, etc. processors
 Instruction set structure
 RISC (Reduced Instruction Set Computer), CISC
(Complex Instruction Set Computer)
 Functions
 General purpose, special purpose such image
processing, floating point calculations
 And more … Week3 4
Typical microprocessors
 Most commonly used
 68K
 Motorola
 x86
 Intel
 IA-64
 Intel
 MIPS
 Microprocessor without interlocked pipeline stages
 ARM
 Advanced RISC Machine
 PowerPC
 Apple-IBM-Motorola alliance
 Atmel AVR
 A brief summary will be given later
Week3 5
Microprocessor applications
 A microprocessor application system can be
abstracted in a three-level architecture
 ISA is the interface between hardware and software

FORTRAN 90 C program
program
FORTRAN 90 C program
program compiled compiled
to ISA program to ISA program
Software
ISA level
Hardware
ISA program executed
by hardware

Hardware

Week3 6
ISA
 Stands for Instruction Set Architecture
 Provides functional specifications for software
programmers to use/program hardware to
perform certain tasks
 Provides the functional requirements for
hardware designers so that their hardware
design (called micro-architectures) can
execute software programs.

Week3 7
What makes an ISA
 ISA specifies all aspects of a computer
architecture visible to a programmer
 Basic
 Instructions
 Instruction format
 Addressing modes
 Native data types
 Registers
 Memory models
 advanced
 Interrupt handling Week3 8

 To be covered in the later lectures

Instructions
 This is the key part of an ISA
 specifies the basic operations available to a
programmer
 Example:
 Arithmetic instructions
 Instruction set is machine oriented
 Different machine, different instruction set
 For example
 68K has more comprehensive instruction set than ARM

Week3 9
Instructions (cont.)
 Instruction set is machine oriented
 Same operation, could be written differently in
different machine
 AVR
 Addition: add r2, r1 ;r2  r2+r1
 Branching: breq 6 ;branch if equal condition is true
 Load: ldi r30, $F0 ;r30  Mem[F0]
 68K:
 Addition: add d1,d2 ;d2  d2+d1
 Branching: breq 6 ;branch if equal condition is true
 Load: mov #1234, D3 ;d3  1234

Week3 10
Instructions (cont.)
 Instructions can be written in two languages
 Machine language
 made of binary digits
 Used by machines
 Assembly language
 a textual representation of machine language
 Easier to understand than machine language
 Used by human beings

Week3 11
Machine code vs. assembly
code
 There is a one-to-one mapping between the
machine code and assembly code
 Example (Atmel AVR instruction):
For increment register 16:
 1001010100000011 (machine code)

 inc r16 (assembly language)

 Assembly language also includes directives
 Instructions to the assembler
 Example:
 .def temp = r16
Week3 12

 .include “mega64def.inc”
Data types
 The basic capability of using different classes of values.
 Typical data types
 Numbers
 Integers of different lengths (8, 16, 32, 64 bits)
 Possibly signed or unsigned
 Commonly available
 Floating point numbers, e.g. 32 bits (single precision) or 64 bits
(double precision)
 Available in some processors such as PowerPC
 BCD (binary coded decimal) numbers
 Available in some processors, such as 68K
 Non-numeric
 Boolean
 Characters
Week3 13
 Data types (cont.)
 Different machines support different data
types in hardware
 e.g. Pentium II:
Data Type 8 bits 16 bits 32 bits 64 bits 128 bits
Signed integer   
Unsigned integer   
BCD integer 
Floating point  

 e.g. Atmel AVR:

Data Type 8 bits 16 bits 32 bits 64 bits 128 bits
Signed integer  Partial
Unsigned integer  Partial
BCD integer
Floating point

Week3 14
Registers
 Two types
 General purpose
 Special purpose
 Used for special functions
 e.g.
 Program Counter (PC)
 Status Register
 Stack pointer (SP)
 Input/Output Registers
 Stack pointer and Input/Output Registers will be
discussed in detail later. Week3 15
General Purpose Registers
 A set of registers in the machine
 Used for storing temporary data/results
 For example
 In (68K) instruction add d3, d5, operands are stored in
general registers d3 and d5, and the result are stored in d5.
 Can be structured differently in different machines
 For example
 Separated general purpose registers for data and address
 68K
 Different numbers registers and different size of each
registers
 32 32-bit in MIPS
Week3 16
 16 32-bit in ARM
Program counter
 Special register
 For storing memory address of currently executed
instruction
 Can be of different size
 E.g. 16 bit, 32 bit
 Can be auto-incremented
 By the instruction word size
 Gives rise the name “counter”

Week3 17
Status register
 Contains a number of bits with each bit
associated with CPU operations
 Typical status bits
 V: Overflow
 C: Carry
 Z: Zero
 N: Negative
 Used for controlling program execution flow

Week3 18
Memory models
 Data processed by CPU is usually large and cannot
be held in the registers at the same time.
 Both data and program code need to be stored in
memory.
 Memory model is related to how memory is used to
store data
 Issues
 Addressable unit size
 Address spaces
 Endianness
 Alignment Week3 19
Addressable unit size
 Memory has units, each of which has an
address
 Most common unit size is 8 bits (1 byte)
 Modern processors have multiple-byte unit
 For example:
 32-bit instruction memory in MIPs
 16-bit Instruction memory in AVR

Week3 20
Address spaces
 The range of addresses a processor can
access.
 The address space can be one or more than one
in a processor. For example
 Princeton architecture or Von Neumann architecture
 A single linear address space for both instructions and data
memory
 Harvard architecture
 Separate address spaces for instructions and data
memories

Week3 21
Address spaces (cont.)
 Address space is not necessarily just for
memories
 E.g, all general purpose registers and I/O
registers can be accessed through memory
addresses in AVR
 Address space is limited by the width of the
address bus.
 The bus width: the number of bits the address is
represented

Week3 22
Endianness
 Memory objects
 Memory objects are basic entities that can be
accessed as a function of the address and the
length
 E.g. bytes, words, longwords
 For large objects (>byte), there are two
ordering conventions
 Little endian – little end (least significant byte)
stored first (at lowest address)
 Intel microprocessors (Pentium etc)
 Big endian – big end stored first
Week3 23
 SPARC, Motorola microprocessors
Endianness (cont.)
 Most CPUs produced since ~1992 are
“bi-endian” (support both)
 some switchable at boot time
 others at run time (i.e. can change dynamically)

Week3 24
Big Endian & Little Endian
 Example: 0x12345678—a long word of 4
bytes. It is stored in the memory at address
0x00000100
Address data
 big endian: 0x00000100 12
0x00000101 34
0x00000102 56
0x00000103 78

Address data
 little endian: 0x00000100 78
0x00000101 56
0x00000102 34
0x00000103
Week3
12 25
Alignment
 Often multiple bytes can be fetched from
memory
 Alignment specifies how the (beginning)
address of a multiple-byte data is determined.
 data must be aligned in some way. For example
 4-byte words starting at addresses 0,4,8, …
 8-byte words starting at addresses 0, 8, 16, …
 Alignment makes memory data accessing
more efficient
Week3 26
Example
 A hardware design that has data fetched from
memory every 4 bytes

 Fetching an unaligned data (as shown)

means to access memory twice.

Week3 27
Instruction format
 Is a definition
 how instructions are represented in binary code
 Instructions typically consist of
 Opcode (Operation Code)
 defines the operation (e.g. addition)
 Operands
 what’s being operated on
 Instructions typically have 0, 1, 2 or 3
operands
Week3 28
Instruction format examples

OpCode OpCode Opd

OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3

Week3 29
Example (AVR instruction)
 Subtraction with carry
 Syntax: sbc Rd, Rr
 Operation: Rd ← Rd – Rr – C
 Rd: Destination register. 0  d  31
 Rr: Source register. 0  r  31, C: Carry
 Instruction format
0 0 0 0 1 0 r d d d d d r r r r
15 0

 OpCode uses 6 bits (bit 9 to bit 15).

 Two operands share the remaining 10 bits.
Week3 30
Instruction lengths
 The number of bits an instruction has
 For some machines – instructions all have
the same length
 E.g. MIPS machines
 For other machines – instructions can have
different lengths
 E.g. M68K machine

Week3 31
Instruction encoding
 Operation Encoding
 2n operations needs at least n bits
 Operand Encoding
 Depends on the addressing modes and access
space.
 For example: An operand in direct register addressing
mode requires at most 3 bits if the the number of
registers it can be stored is 8.
 With a fixed instruction length, more encoding
of operations means less available bits for
encoding operands
Week3 32
 Tradeoffs should be concerned
Example 1
 A machine has:
 16 bit instructions
 16 registers (i.e. 4-bit register addresses)
 Instructions could be formatted like this:

OpCode Operand1 Operand2 Operand3

 Maximally 16 operations can be defined.

 But what if we need more instructions and some
instructions only operate on 0, 1 or 2 registers?
Week3 33
Example 2
 For a 16 bit instruction machine with 16
registers, design OpCodes that allow for
 14 3-operand instructions
 30 2-operand instructions
 30 1-operand instructions
 32 0-operand instructions

Week3 34
Addressing modes
 Instructions need to specify where to get operands from
 Some possibilities
 Values are in the instruction
 Values are in the register
 Register number is in the instruction
 Values are in memory
 address is in instruction
 address is in a register
 register number is in the instruction
 address is register value plus some offset
 register number is in the instruction
 offset is in the instruction (or in a register)
 These ways of specifying the operand locations are called
addressing modes
Week3 35
Immediate Addressing
 The operand is from the instruction itself
 I.e the operand is immediately available from the
instruction
 For example, in 68K
addw #99, d7

 Perform d7  99 + d7; value 99 comes from the

instruction
 d7 is a register Week3 36
Register Direct Addressing
 Data from a register and the register number
is directly given by the instruction
 For example, in 68K
addw d0,d7
 Perform d7  d7 + d0; add value in d0 to value in d7
and store result to d7
 d0 and d7 are registers

Week3 37
Memory direct addressing
 The data is from memory, the memory
address is directly given by the instruction
 We use notion: (addr) to represent memory
value with a given address, addr
 For example, in 68K
addw 0x123A, d7

 Perform d7  d7 + (0x123A); add value in memory

location 0x123A to register d7
Week3 38
Memory Register Indirect
Addressing
 The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction
 For example, in 68K
addw (a0),d7
 Perform d7  d7 + (a0); add value in memory
with the address stored in register a0, to register
d7
 For example, if a0 = 100 and (100) = 123, then this
adds 123 to d7 Week3 39
Memory Register Indirect
Auto-increment
 The data is from memory, the memory
address is given by a register, which is
directly given by the instruction; and the value
of the register is automatically increased – to
point to the next memory object.
 Think about i++ in C
 For example, in 68K
addw (a0)+,d7

 d7  d7 + (a0); a0  a0 + 2
Week3 40
Memory Register Indirect
Auto-decrement
 The data is from memory, the memory
address is given by a register and the register
number is directly given by the instruction;
but the value of the register is automatically
decreased before such an operation.
 Think --i in C
 For example, in 68K
addw -(a0),d7

 a0  a0 –2; d7  d7 + (a0);
Week3 41
Memory Register Indirect with
Displacement
 Data is from the memory with the address
given by the register plus a constant
 Used in the access of a member in a data
structure
 For example, in 68K
addw a0@(8), d7

 d7  (a0+8) +d7

Week3 42
Address Register Indirect with
Index and displacement
 The address of the data is sum of the initial address
and the index address as compared to the initial
address plus a constant
 Used in accessing element of an array
 For example, in 68K
addw a0@(d3)8, d7

 d7  (a0 + d3+8)
 With a0 as an initial address and d3 as an index
dynamically pointing to different elements, plus a constant
for a certain member in an array element.
Week3 43
RISC
 RICS stands for reduced instruction set
computer
 Smaller and simpler set of instructions
 Smaller: small number of instructions in the instruction
set
 Simpler: instruction encoding is simple
 Such as fixed instruction length
 All instructions take about the same amount of
time to execute

Week3 44
CISC
 CISC stands for complex instruction set
computer
 Each instructions can execute several low-level
operations
 Such operations of load memory, arithmetic and store
memory in one instructions
 Required complicated hardware support
 All instructions take different amount of time to
execute

Week3 45
Recall: Typical processors
 Most commonly implemented in hardware
 68K
 Motorola
 x86
 Intel
 IA-64
 Intel
 MIPS
 Microprocessor without interlocked pipeline stages
 ARM
 Advanced RISC Machine
 PowerPC
 Apple-IBM-Motorola alliance
Week3 46

 Atmel AVR
X86
 CISC architecture
 16 bit  32-bit  64-bit
 Words are stored in the little endian order
 Allow unaligned memory access.
 Current x86-processors employs a few “extra”
decoding steps to (during execution) split (most) x86
instructions into smaller pieces (micro-instructions)
which are then readily executed by a RISC-like
micro-architecture.
 Application areas (dominant)
 Desktop, portable computer, small servers
Week3 47
68K
 CISC processor
 Early generation, hybrid 8/16/32 bit chip (8-bit
bus)
 Late generation, fully 32-bit
 Separate data registers and address registers
 Big endian
 Area applications
 Early used in for calculators, control systems,
desktop computers
 Later used in microcontroller/embedded
Week3 48

microprocessors.
MIPS
 RISC processor
 A large family designs with different configurations
 Deep pipeline (>=5 stages)
 With additional features
 Clean instruction set
 Could be booted either big-endian or little-endian
 Many application areas, including embedded
systems
 The design of the MIPS CPU family, together with
SPARC, another early RISC architecture, greatly
influenced later RISC designs
Week3 49
ARM
 32-bit RISC processor
 Three-address architecture
 No support for misaligned memory accesses
 16 x 32 bit register file
 Fixed opcode width of 32 bit to ease decoding and
pipelining, at the cost of decreased code density
 Mostly single-cycle execution
 With additional features
 Conditional execution of most instructions
 reducing branch overhead and compensating for the lack of
a branch predictor
 Powerful indexed addressing modes
Week3 50
 Power saving
PowerPC
 Superscalar RISC
 32-bit, 64-bit implementation
 With both big-endian and little endian modes,
can switch from one mode to the other at run-
time.
 Intended for high performance PC, for high-
end machines

Week3 51
Reading Material
 Chap.2 in Microcontrollers and
Microcomputers.

Week3 52
Questions
1. Given an address bus width in a
processor as 16-bit, determine the
maximal address space.
2. Assume a memory address is 0xFFFF,
how many locations this address can
represent if the related computer is?
I) a Harvard machine
II) a Von Neumann machine
Week3 53