Concepts in VLSI Design

Presented by
Niket Agrawal
(MTech VLSI)

IIT Guwahati
 What is a transistor (Digital Definition)

A Switch! An MOS Transistor

VGS  V T |VGS|

Ron
S D
The NMOS Transistor
Threshold Voltage: Concept

+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

B
Transistor in Linear

VGS VDS
S
G ID
D

n+ – + n+
V(x)

L x

p-substrate

MOS transistor and its bias conditions

Transistor in Saturation

VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off
Current-Voltage Relations
Long-Channel Device
Current-Voltage Relations
-4
x 10
6
VGS= 2.5 V

4
Resistive Saturation
VGS= 2.0 V
Quadratic
ID (A)

3
VDS = VGS - VT Relationship

2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
V DS (V)
Velocity Saturation
( Deep sub micron Era)
u n (m/s)

usat = 105
Constant velocity

Constant mobility (slope = µ)

xc = 1.5 x (V/µm)
Perspective

ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

ID versus VGS
-4 -4
x 10 x 10
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

A unified model
for manual analysis
A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8 VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
MOS Capacitances
G

CGS CGD

S D

CSB CGB CDB

B
The Gate Capacitance
Poly silicon gate

Source Drain
W
n+ xd xd n+

Gate-bulk
Ld
overlap
Top view

Gate oxide
tox
n+ L n+

Cross section
 Gate Capacitance
G G G

CGC CGC CGC

S D S D S D

Cut-off Resistive Saturation

Most important regions in digital design: saturation and cut-off

Diffusion Capacitance
Channel-stop implant
N A1

Side wall
Source
W
ND

Bottom

xj Side wall
Channel
LS Substrate N A
 Sub-Threshold Region (MOS now a BJT)

-2
10

Linear qVGS
CD
I D ~ I 0e , n 1 
-4
10
nkT
10
-6
Quadratic Cox
ID (A)

-8
10

-10 Exponential
10

-12
VT
10
0 0.5 1 1.5 2 2.5
VGS (V)
Fabrication
 For a great tour through the IC
manufacturing process
and its different steps, check
http://www.fullman.com/semiconduct
ors/semiconductors.html
CMOS Process at a Glance
Define active areas
Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers
Inverter Layout
VDD

PMOS
In Out

NMOS

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
 Fabrication Steps
 Start with blank wafer (typically p-type where
NMOS is created)
 First step will be to form the n-well (where
PMOS would reside)
 Cover wafer with protective layer of SiO2 (oxide)
 Remove oxide layer where n-well should be built
 Implant or diffuse n dopants into exposed wafer to
form n-well
 Strip off SiO2

p substrate
Oxidation

 Grow SiO2 on top of Si wafer

 900 – 1200 C with H2O or O2 in oxidation
furnace

SiO2

p substrate
Photoresist
 Photo resist
 Photoresist is a light-sensitive organic
polymer
 Property changes where exposed to light

 Two types of photo resists (positive or

negative)
 Positive resists can be removed if exposed
to UV light
 Negative resists cannot be removed if
exposed to UV light
Photoresist
SiO 2


p substrate
Lithography
 Expose photoresist to Ultra-violate
(UV) light through the n-well mask
 Strip off exposed photo resist with
chemicals

Photoresist
SiO 2

p substrate
Etch

 Etch oxide with hydrofluoric acid (HF)

 Only attacks oxide where resist has been
exposed
 N-well pattern is transferred from the mask to
silicon-di-oxide surface; creates an opening to
the silicon surface

Photoresist
SiO 2

p substrate
Strip Photoresist

 Strip off remaining photoresist

 Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in
next step

SiO2

p substrate
N-well
 N-well is formed with diffusion or ion implantation
 Diffusion
 Place wafer in furnace with arsenic-rich gas

 Heat until As atoms diffuse into exposed Si

 Ion Implanatation
 Blast wafer with beam of As ions

 Ions blocked by SiO2, only enter exposed Si

 SiO2 shields (or masks) areas which remain p-type

SiO2

n well
Strip Oxide

 Strip off the remaining oxide using HF

 Subsequent steps involve similar
series of steps

n well
p substrate
Poly silicon
(self-aligned gate technology)
 Deposit very thin layer of gate oxide
 < 20 Å (6-7 atomic layers)

 Chemical Vapor Deposition (CVD) of silicon

layer
 Place wafer in furnace with Silane gas
(SiH4)
 Forms many small crystals called polysilicon

 Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate
Self-Aligned Process

 Use gate-oxide/poly silicon and

masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain,
and n-well contact

n well
p substrate
N-diffusion/implantation

 Pattern oxide and form n+ regions

 Self-aligned process where gate blocks n-
dopants
 Polysilicon is better than metal for self-aligned
gates because it doesn’t melt during later
processing

n+ Diffusion

n well
p substrate
N-diffusion/implantation cont.

 Historically dopants were diffused

 Usually high energy ion-implantation
used today
 But n+ regions are still called diffusion

n+ n+ n+
n well
p substrate
P-Diffusion/implantation

 Similar set of steps form p+

“diffusion” regions for PMOS source
and drain and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate
Contacts

 Now we need to wire together the

devices
 Cover chip with thick field oxide (FO)
 Etch oxide where contact cuts are
needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate
 Metalization

 Sputter on aluminum over whole wafer

 Gold is used in newer technology
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
 CMOS INVERTER
VDD V DD V DD

Rp
PMOS
In Out V out
V out

Rn
NMOS

V in 5 V DD V in 5 0
 CMOS Inverter VTC
Vout VDD
NMOS off
PMOS res
2.5

NMOS s at
PMOS res PMOS
2

In Out
NMOS sat
1.5

PMOS sat

NMOS
1

NMOS res
PMOS sat NMOS res
0.5

PMOS off

0.5 1 1.5 2 2.5 Vin

CMOS Inverter Propagation Delay

VDD

tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout ln(0.5)
CL
1 VDD
Ron

0.5
0.36

Vin = V DD
t
RonCL
 Transient Response
3

2.5
?
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
Vout(V)

tpLH tpHL
1

0.5

-0.5
0 0.5 1 1.5 2 2.5
t (sec) -10
x 10
Design for Performance

 Keep capacitances small

 Increase transistor sizes
 watch out for self-loading!
 Increase VDD (???)
Delay as a function of VDD

5.5

4.5

4
tp(normalized)

3.5

2.5

1.5

1
0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
V (V)
DD
 Delay as a function of Device Sizing

-11
3.8
x 10 (for fixed load)

3.6

3.4

3.2

Self-loading effect:
tp(sec)

3
Intrinsic capacitances
2.8
dominate
2.6

2.4

2.2

2
2 4 6 8 10 12 14
S
Where Does Power Go in CMOS?

• Dynamic Power Consumption

Charging and Discharging Capacitors

• Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

• Leakage
Leaking diodes and transistors
Dynamic Power Dissipation
Vdd

Vin Vout

CL

2
L dd
Energy/transition = C * V 2
L dd
Power = Energy/transition * f = C * V *f
Short Circuit Currents
Vd d

Vin Vout

CL

0.15

0.10
IVDD (mA)

0.05

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)
Leakage
Vd d

Vout

Drain Junction
Leakage

Sub-Threshold
Current

Sub-threshold current one of most compelling issues

Sub-Threshold
in low-energy circuitCurrent
design!Dominant Factor
Principles for Power Reduction
 Prime choice: Reduce voltage!
 Recent years have seen an acceleration in
supply voltage reduction
 Design at very low voltages still open
question (0.6 … 0.9 V by 2010!)
 Reduce switching activity
 Reduce physical capacitance
Goals of Technology Scaling

 Make things cheaper:

 Want to sell more functions (transistors)
per chip for the same money
 Build same products cheaper, sell the
same part for less money
 Price of a transistor has to be reduced
 But also want to be faster, smaller,
lower power
Static CMOS Circuit

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Static Complementary CMOS
VDD

In1
PMOS only
In2 PUN
InN
F(In1,In2,…InN)
In1
In2 PDN
NMOS only
InN

PUN and PDN are dual logic networks

Threshold Drops
VDD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D
Example Gate: NAND
Complex CMOS Gate

B
A
C

D
OUT = D + A • (B + C)
A
D
B C
CMOS Properties
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power
and ground; no static power dissipation
 Propagation delay function of load capacitance
and resistance of transistors
 Delay Dependence on Input Patterns

3
Input Data Delay
2.5 A=B=10 Pattern (psec)
2 A=B=01 67
A=1 0, B=1
A=1, 64
Voltage [V]

1.5
B=01
1
A=1, B=10
A= 01, 61
B=1
0.5
A=B=10 45
0
0 100 200 300 400 A=1, 80
-0.5 B=10
time [ps] A= 10, 81
B=1
Fast Complex Gates:
Design Technique 1

 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
Fast Complex Gates:
Design Technique 2
 Transistor ordering
critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL
Summary

 It was a big talk

 At last it finished
 Now I Want to enjoy Sunday