EDA Introduction

Professor: Sci.D., Prof. Vazgen

Melikyan

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Course Overview

 Introduction
 1 lecture
 IC Design Data Formats and Tools
 4 lectures
 Electronic Design Methodology
 4 lectures
 IC Synthesis
 2 lectures
 Databases for EDA
 3 lectures
 IC Design Approaches and Flows
 3 lectures
 EDA Tools
 3 lectures
 Overview of Synopsys EDA Tools
 3 lectures

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IC Synthesis

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Synthesis Problem

 Synthesis is an automated process which, from the

perspective of the user of the device that is being
designed, translates the written hardware description
into logic structural description.
 If a text file, written in some HDL language is used for
design description, the synthesis is called HDL
synthesis. In this case the synthesis problem is to
translate HDL description into real hardware description
 Synthesis tool generates gate level netlist for target
technology

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Synthesis Problem (2)

 Synthesis consists of two stages:

 Translation
 Optimization

x <= ( a and b ) or ( c and d );

a a a
b b
b
x x LUT x
c
c c
d d d

 Synthesis assumes use of target devices for some technology

 Synthesis tool tries to use the best architectural resource for the given target devices

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Synthesis Steps

 Translation (language synthesis):

Hardware Description -
compiling description on high-level Translation written with hardware in
design, based on the elements of mind
a famous language
 Optimization: reduction of
hardware means of the design Mix of Boolean, other
and use of algorithms to increase Optimization operations and memory
performance. elements
 Mapping: the design is mapped
into definite technical means
architecture. Gate Level –
Mapping Technology Specific

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Synthesis Flow
HDL behavioral
Netlist
description

RTL Synthesis
RTL Optimization Logic extraction Translation means that translate Boolean
equations into gate level netlists
High-level
Structured
description
Boolean
with Boolean
equation
equation
Technology-invariant logic optimization
Logic Optimization

Optimization of logic structure. Elimination of

Structured redundant logic and reduction of necessary area
Boolean
equation

Technology Transition from technology-independent netlist into

mapping Gate-level
optimization technology-specific netlist
 Flattening
 Structuring
Optimized
Netlist

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Flattening

 Flattening goal is to generate Boolean equations in such

a way that the output value is a direct function of inputs.
 These equations reflect two-level logic in the form of
standard operations.
 In the result, equations do not assume any particular
structure.
 Equations can undergo efficient optimization.
 Can lead to elimination of inherent structures and their
related properties.
 Cannot be applied on large circuits.
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Structuring

 Structuring is the opposite of flattening and is aimed at embedding

such intermediate nodes in the general structure of the design which
will replace the repetitive factors.
 Addition of intermediate variables in flat Boolean equations.
 For example, if in flat equation (А v B v С) expression is met n times,
then X = (А v B v С) expression can be calculated once and use X in
all n places of flat equation.
 As a result, putting subfunctions in the initial flat equation, will lead
to the reduction of area of the device, being designed.

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Summarizing Synthesis Process

Design Constraint Libraries

(area, performance)

Synthesis
Steps Methodology
 Translation process converts  Flattening
RTL to a Boolean form  Structuring
 Optimization is done on the
converted Boolean equations
 Optimized logic is mapped to
technology library

Netlist Report

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Requirements to Synthesis Tools

 Possibility of technology-specific optimization

 Possibility of controlling synthesis process by the
designer
 Language provision
 Provision of comfortable setup environment
 Provision of compilation performance
 Compatibility with simulation tools
 Presence of efficient interface, connecting to other tools

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Characteristics of Synthesis Tools

 The value of the tool is conditioned by target capabilities

it offers.
 Desired capabilities are:
 Replicate logic
 Multi-replication of flip-flops and exclusion of not used logic
 Hierarchical optimization of the design
 Joint usage of resources of different functional nodes (adders,
incrementors, multipliers)
 Automated reflection of RAM memory logic in technological structures of
memory cells

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Concept-to-Silicon Design Flow
High Level Design
Algorithms and
Concept Architecture
DSP

Automated Design Verification Custom Design

Description in Logic simulation
HDL Specification

Logic Synthesis Equivalence Circuit

checks
and Optimization design

Gate Level Transistor Level Transistor

Timing analysis
circuit Simulation Level Circuit

Physical Layout vs. Physical

Synthesis Schematic check Design

Design Rule Physical

Physical design checks design

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High-level Synthesis (1)
 High-level synthesis is the process of mapping a behavioral
description at the algorithmic level to a structural
description in terms of functional units, memory elements
and interconnections (e.g. multiplexers and buses).
Behavioral domain Structural domain
Systems Processor
Algorithms Functional units
Register transfers ALU’s, RAM, etc.
Logic Gates, flip-flops, etc.
Transfer functions Transistor
Transistor layout
Cell layout
Module layout
Floorplan
Physical partitions
Physical domain
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High-Level Synthesis (2)

 Creates RTL High-Level

 Uses Synthesis
 Signal processing models
 Fixed-point algorithms RTL
 IP TLM models from vendor
 Enables Logic
 Optimized FPGA and ASIC implementations Synthesis
 Prototypes and simulators for verification
 Early software/system validation Netlist
 Reduction of effort and lower risk

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High-level Synthesis (3)

Aspects of high-level synthesis

 Definition of hardware models

 Before mapping an algorithm to hardware, one should define the type of the target hardware.

 The formal description of the algorithm to be mapped

 Most high-level synthesis systems use some sort of data-flow graph for this purpose.

Type of circuits

 Combinational Synchronous or clocked circuits

 Sequential Asynchronous

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Steps of High-level Synthesis

Lexical processing
Lexical processing analyses behavior description, presented by high level language and
changes it into internal description.
The task of hardware models
Before mapping an algorithm to hardware, one should define the type of the target hardware.
All restrictions together define a high-level synthesis system's hardware model, the type of
hardware that the system is able togenerate.
Internal Representation of the Input Algorithm
It is almost generally agreed that this representation should be graph based. The graph that
is used to represent an algorithm is called a data-flow graph (DFG).
Allocation, Assignment and Scheduling
Allocation simply reserves the hardware resources that will be necessary to realize the
algorithm. Assignment maps each operation in the DFG to a specific functional unit on
which the operation will be executed. Scheduling is the task of determining the instants at
which the execution of the operations in the DFG will start.

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 Logic Synthesis
Logic synthesis is concerned with the generation and optimization of a
circuit at the level of Boolean gates.
Behavioral domain Structural domain
Systems Processor
Algorithms Functional units
Register transfers
ALU’s, RAM, etc
Logic Gates, flip-flops, etc.
Transfer functions Transistor

Transistor layout
Cell layout
Module layout
Floorplan
Physical partitions The Synthesis Flow
Physical domain
1. Specify the function (usually by means of truth tables and equations)
2. Boolean functions minimization. Getting equations
3. Create a circuit corresponding to the outputs’ equations
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Logic Synthesis Input and Output

Starts from a register-transfer level (RTL) description,

given in e.g. VHDL or given as a set of Boolean
expressions.

Three different tasks: two-level combinational synthesis,

multilevel combinational synthesis and sequential
synthesis.

Outputs a standard-cell netlist or some other form of

realization such as a PLA.

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Logic Synthesis Steps
Design RTL description
residue = 16’h0000;
if (high_bits == 2’b10)
Technology Specific residue = state_table[index];
Circuit is obtained from else
independent one by Translation state_table[index] = 16’h0000;
replacing all components
by real blocks (standard
cells). This replacement
process is also called Technology Independent
mapping Circuit

Compilation
and Optimization Technology Independent
4x Circuit is a logic circuit
3x which fully implements
2x 8x
function described but is
Technology Specific built from Generic
1x 2x Circuit Boolean Gates.

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Circuit Level Design Tasks

Circuit level design deals with the formation of descriptions

of designed IC at the transistor level and consists of
separate design procedures.
Typical circuit level design procedures are:
 Analysis of designed circuits

 Synthesis of designed circuits

 Optimization, which leads to optimal (according to

certain criteria) design solution

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Circuit Level Design Flow
Specification

Schematic Design
Transistor-level
Symbol Creation Design Tools
Simulation
Pre-layout
Layout Design verification tools
Physical Verification (DRC/LVS) Post-layout
verification and
Parasitic Extraction extraction tools

Resimulation with parasitics

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Circuit Level Analysis Problem

 The analysis procedure is to determine the properties of

a given description of designed circuit.
 The calculation of frequency and transient response of
electronic circuits, the definition of circuit's response to a
given exposure, etc can serve as an example of such a
procedure.
 Analysis allows estimating the degree of satisfaction of
design solutions to specified requirements and its
suitability.

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Circuit Level Synthesis Problem

 Synthesis procedure is to create a design solution

(description) of specified requirements, properties and
restrictions.
 For example, synthesis procedures of electronic circuits
on their specified characteristics in the frequency or time
domain are widely used.
 Two types of synthesis:
 Selection of structural circuit, called structural synthesis
 Definition of parameters of its elements (which provide the required
characteristics), called parametric synthesis.

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Circuit Level Optimization Problem

 Optimization procedure leads to optimal (according to

certain criteria) design solution.
 For example, parameter optimization of electronic
circuits aimed at best approximation of the frequency
characteristics of a given ones is widely used.
 Optimization procedure is a repeated analysis of a target
change of parameters of a circuit to a satisfactory
approximation to a given characteristic.

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Physical Synthesis Steps
Floorplanning

Global placement

Placement

Clock Tree Synthesis

Global Routing

Detailed Routing

Sign-off

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New Trends in Physical Design Cycle

 There are many new trends in the industry, which seek to

significantly alter the IC design flow. The major contributing factors
are:
 Increasing interconnect delay
 Increasing interconnect area
 Increasing number of metal layers
 Increasing planning requirement
 Synthesis
 As a result, in high performance chips, interconnect delay must be
considered from very early design stages. To reduce interconnect
delay, several methods can be employed:
 Chip level signal planning
 Over-the-cell routing

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Significance of Physical Design

 Many existing solutions are still very suboptimal

 E.g. placement
 Interconnect dominates
 No physical layout, no accurate interconnect
 More new physical and manufacturing effects pop up
 Crosstalk noise, etc.
 OPC (manufacturability), etc.
 More vertical integration needed
 Physical design is the key linking step between higher
level planning/optimization and lower level modeling

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