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Sram Memory Cell

The document discusses SRAM memory cells and their operation. It provides details on 6T SRAM cells, including how they store data using cross-coupled inverters. It describes SRAM read and write operations, and how wordlines and bitlines are used. It also discusses static noise margin, which is a measure of voltage noise required to flip a cell's contents, and how this impacts SRAM design and voltage scaling.

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Sathyanarayana Rao
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© © All Rights Reserved
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68 views

Sram Memory Cell

The document discusses SRAM memory cells and their operation. It provides details on 6T SRAM cells, including how they store data using cross-coupled inverters. It describes SRAM read and write operations, and how wordlines and bitlines are used. It also discusses static noise margin, which is a measure of voltage noise required to flip a cell's contents, and how this impacts SRAM design and voltage scaling.

Uploaded by

Sathyanarayana Rao
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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SRAM Memory Cell

BY SHEERUN
Objective
 6T memory cell operation
 Hold state

 Read operation

 Write operation

 Bit Cell Transistor sizing


 Bit Cell stability
 Static Noise Margin

-2-
Memory Arrays
3

Memory Arrays

Random Access Memory Serial Access Memory Content Addressable Memory


(CAM)

Read/Write Memory Read Only Memory


Shift Registers Queues
(RAM) (ROM)
(Volatile) (Nonvolatile)

Serial In Parallel In First In Last In


Static RAM Dynamic RAM Parallel Out Serial Out First Out First Out
(SRAM) (DRAM) (SIPO) (PISO) (FIFO) (LIFO)

Mask ROM Programmable Erasable Electrically Flash ROM


ROM Programmable Erasable
(PROM) ROM Programmable
(EPROM) ROM
(EEPROM)
Static RAM (SRAM)
4

 Static Random Access Memory (SRAM) is


a type of semiconductor memory where the
word static indicates that, unlike dynamic RAM
(DRAM), it does not need to be periodically
refreshed, as SRAM uses bistable latching
circuitry to store each bit.
 A typical SRAM uses six MOSFETs to store each
memory bit
 These transistors are made as small as possible
to save chip-area, and are very weak
Advantages of 6T SRAM cell
5

 Low static power dissipation


 Superior noise margins
 High switching speeds
 Once value is written, it is guaranteed to remain in
the memory as long as power is applied
 Suitability for high-density SRAM arrays
6T SRAM Cell
6

 Cell size accounts for most of array size


 Reduce cell size at expense of complexity

 6T SRAM Cell
 Data stored in cross-coupled inverters

bit bit_b
word
SRAM operations
7
Stable Configurations

0 1 1 0 Set Wordline to Low

 Read:
 Precharge bit, bit_b
 Raise wordline

 Write:
 Drive data onto bit, bit_b
 Raise wordline, and the strong bitline input-drivers
 The value inside the SRAM cell is overwritten because the
transistors inside the SRAM cell are very weak.
SRAM Read

 Precharge both bitlines high


 Then turn on wordline
 One of the two bitlines will be pulled down by the
cell
 Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high
– But A bumps up slightly
 Read stability
– A must not flip
– N1 >> N2
Read cycle
9

•tRC (time of read cycle)

•tCEA moments from circuit


enabled, data are read being
available atthe data pins of
that circuit

tRA, access time for read


operation,
SRAM Write
10

 Drive one bitline high, the other low


 Then turn on wordline
 Bitlines overpower cell with new value
 Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high
 Writability
– Must overpower feedback inverter
– N2 >> P1
Write Cycle
11
 tWC(time related tothe write cycle)
 tCES Chip enable signal
 tAS address enabled moment:
time needed for a correct setup
of address lines
 tDS gives the difference between
start of data availability and disable
moment of read/write command signal
 tDH or the time needed to maintain
data for acorrect write operation
 tCEH how long time to maintain
CE- signal after the write command signal
is no more valid
 tAH, or how long to maintain addresses
valid, after the write command is off
SRAM Sizing
12

 High bitlines must not overpower inverters during


reads
 But low bitlines must write new value into cell

bit bit_b
word
weak
med med
A A_b
strong
Static Noise Margin
13

 The large fraction of chip area often devoted to SRAM makes low power
SRAM design very important.
 SNM quantifies the amount of voltage noise required at the internal
nodes of a bitcell to flip the cell’s contents.
 degraded SNM can limit voltage scaling for SRAM designs.

BL WL BLB

M3
VN
M6
SNM is length of side of the
M2
M5 largest embedded square on
M1 M4
Q VN QB the butterfly curve
Inverter 1 Inverter 2

 Note: SNM butterfly is plot of the storage node voltage during write. So write a '1' to the cell and plot Node Q vs Node QB. The write a '0' and plot Node Q vs QB
on the same plot. You can then measure the SNM as the largest square that fits inside the butterfly curve.
Butterfly diagram
14
Static Noise Margin(Cont’d)
15

The minimum supply voltage of SRAMs is determined by both Read SNM and Write SNM levels;
reducing Vth in the NMOS transistor improves Write SNM but worsens Read SNM.

Moves to the left

Moves upward

SNM Butterfly Curve

SNM is lower during read access because the VTC is


degraded by the voltage divider across the access
transistor (M2,M5) and drive transistor (M1,M4)
SNM during HOLD and READ
16
BL BLB BL prech 1 BLB prech 1
WL=0 WL=1
M3 M6 M3 M6
M2 M2
M5 M5
M1 M4 M1 M4
1 0 [1] 1 0

Read SNM is worst-case


A read SNM free SRAM
17

 decreases in Read SNM in conventional SRAM cells:

 When SNM>0mV, stable data retention is still achieved even


though the voltage at Node V1 may slightly exceed “0”.

 When SNM<0mV, however, reversal data is overwritten.

1) Node V1 voltage greatly exceeds “0”.


2) Node V2 voltage falls below “1” because Node V1 voltage reaches
the CMOS inverter logic threshold voltage (P2, N2).
3) The fall in Node V2 voltage raises Node V1 voltage further
resulting in the overwriting of reversal data.
[3]
Cont’d
18

[3]
Sub-VT SNM Dependencies
19

 SNM is mainly a function of:


 Vdd (limited to Vdd/2)
 Temperature (higher temp results in
Lower SNM due to lower gain)
 Sizing (Cell ratio affects SNM less in
sub-threshold due to logarithmic relation
unless it affects Vt)
 Bit-line voltage
 Vt mismatch Vt mismatch is the worst
Thanks
20

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