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Arm Architecture

The ARM architecture is a 32-bit RISC processor with 37 integer registers, including 16 general purpose registers. It uses a pipelined, cached, and Von Neuman or Harvard bus structure depending on the implementation. The ARM7 core has 3 pipeline stages and supports 8, 16, and 32-bit data types across 7 operating modes. The ARM architecture aims to achieve a reasonably good balance of speed and power consumption through its simple structure and instruction set.

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111 views

Arm Architecture

The ARM architecture is a 32-bit RISC processor with 37 integer registers, including 16 general purpose registers. It uses a pipelined, cached, and Von Neuman or Harvard bus structure depending on the implementation. The ARM7 core has 3 pipeline stages and supports 8, 16, and 32-bit data types across 7 operating modes. The ARM architecture aims to achieve a reasonably good balance of speed and power consumption through its simple structure and instruction set.

Uploaded by

shettysharath007
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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ARM architecture

 32-bit RISC-processor core (32-bit instructions)


 37 pieces of 32-bit integer registers (16 available)
 Pipelined (ARM7: 3 stages)
 Cached (depending on the implementation)
 Von Neuman-type bus structure (ARM7), Harvard (ARM9)
 8 / 16 / 32 -bit data types
 7 modes of operation (usr, fiq, irq, svc, abt, sys, und)
 Simple structure -> reasonably good speed / power consumption ratio
Instruction sets
ARM7TDMI Block Diagram
Registers

 37 registers
 31 general 32 bit registers, including PC
 6 status registers
 15 general registers (R0 to R14), and one status registers and program counter are
visible at any time –when you write user-level programs
o R13 (SP)
o R14 (LR)
o R15 (PC)
 The visible registers depend on the processor mode
 The other registers (the banked registers) are switched in to support IRQ, FIQ,
Supervisor, Abort and Undefined mode processing
Thank You

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