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Fabrication of CMOS Integrated Circuits

The document describes the key steps in fabricating CMOS integrated circuits, including wafer preparation through crystal pulling and slicing, thin film deposition processes, and front-end processes like photolithography, ion implantation, and etching. It provides details on polysilicon refining, crystal pulling, wafer slicing and polishing, and oxidation processes. It also includes illustrations of process steps for a basic n-well CMOS process with single metal layer and double poly, showing cross-section views of masks for n-well, active, poly1, poly2, p-select, contact, and metal1 layers.

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Vinay Goddemme
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205 views56 pages

Fabrication of CMOS Integrated Circuits

The document describes the key steps in fabricating CMOS integrated circuits, including wafer preparation through crystal pulling and slicing, thin film deposition processes, and front-end processes like photolithography, ion implantation, and etching. It provides details on polysilicon refining, crystal pulling, wafer slicing and polishing, and oxidation processes. It also includes illustrations of process steps for a basic n-well CMOS process with single metal layer and double poly, showing cross-section views of masks for n-well, active, poly1, poly2, p-select, contact, and metal1 layers.

Uploaded by

Vinay Goddemme
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Fabrication of CMOS

Integrated Circuits
CHAPTER 4
John P. Uyemura
Wafer Preparation
Wafer
Design
Preparation

• Polysilicon Refining Thin Films


Front-End
Processes

• Crystal Pulling Photo-


lithography
• Wafer Slicing & Polishing
• Epitaxial Silicon Ion
Implantation
Etch

Deposition
Cleaning Planarization

Test &
Assembly
Polysilicon Refining

Chemical Reactions
Silicon Refining: SiO2 + 2 C  Si + 2 CO
Silicon Purification: Si + 3 HCl  HSiCl3 + H2
Silicon Deposition: HSiCl3 + H2  Si + 3 HCl

Reactants
H2
Silicon Intermediates
H2SiCl2
HSiCl3
Crystal Pulling
Quartz Tube
Rotating Chuck
Seed Crystal
Process Conditions
Flow Rate: 20 to 50 liters/min Growing Crystal
Time: 18 to 24 hours (boule)
Temperature: >1,300 degrees C
Pressure: 20 Torr

RF or Resistance
Heating Coils
Materials
Polysilicon Nodules * Molten Silicon
Ar * (Melt)
H2 Crucible

* High proportion of the total product use


Wafer Slicing & Polishing
silicon wafer

p+ silicon substrate

The silicon ingot is grown and


individual wafers are sliced.

The silicon ingot is sliced into


individual wafers, polished, and
cleaned.

3/15/98 PRAX01C.PPT Rev. 1.0


OXIDATION PROCESS IN
FABRICATION
WHAT IS OXIDATION?
• It is a way to produce a layer of Silicon
dioxide on the surface of a wafer
• Normally referred to as “Thermal
Oxidation”
• Process is done at very high temperatures
• Two types
– Dry Oxidation
– Wet Oxidation
WHY SiO2 ?
• Has excellent dielectric properties
• One among the best insulators
• Relatively easy to obtain when compared
to other insulators
• Unwanted SiO2 can be removed selectively
to Si without any problems
• It is very stable and chemically inert
• SiO2 is normally used
– As Gate oxides (thin layer insulating the gate
and channel area)
– For electrical isolation between different layers
on the chip
– For Masking
– As Field oxides (thick layer insulating the
device from other devices on the chip)
– For Passivation
OXIDATION PROCESS
DRY OXIDATION
• Requires temperature of 8000C to 11000C
• Slow process (about 10 hours for 700nm
oxide)
• Easily controllable
• Si + O2  SiO2
• Pure high quality oxide
• Used for Gate oxide
WET OXIDATION
• Inlet gas is a mixture of water vapor and
oxygen
• Si + 2H2O  SiO2 + 2H2
• Nearly 10 times faster than dry oxidation
• Temperatures of 7000C to 12000C
• Medium quality oxide
• Used for obtaining Field oxide
CVD
• Chemical vapour deposition (CVD) is used
where Si cannot be directly oxidized
• Wafer (substrate) is exposed to volatile
compounds (called precursors)
• These react and decompose on the
substrate and produce the desired deposit
• CVD can also be used for deposition of
– Polycrystalline Silicon
– Silicon Nitride
Detailed Description of First
Photolithographic Steps Only

• Top View
• Cross-Section View
C D

A A’

B B’

C’ D’
A A’

B B’
A A’

B B’
Bulk CMOS Process
Description
• N-well process
• Single Metal Only Depicted
• Double Poly
A A’
D

G B
S
D
B S B’

n-channel MOSFET G
A A’
D

G B
S

B B’
W L
A A’

Capacitor Resistor

p-channel MOSFET

B B’

n-channel MOSFET
N-well Mask

A A’

B B’
N-well Mask

A A’

B B’
Blank Wafer
Implant
n-well
Photoresist
Mask
A A’
p-doped Substrate

B B’
Develop
Expose
Develop
N-well
Exposure
Photoresist
Mask

A-A’ Section

B-B’ Section
Implant

A-A’ Section

B-B’ Section
N-well Mask

A-A’ Section

B-B’ Section
Active Mask

A A’

B B’
Active Mask

A A’

B B’
Active Mask
Field Oxide

A-A’ Section

Field Oxide Field Oxide Field Oxide

B-B’ Section
Poly1 Mask

A A’

B B’
Poly1 Mask

A A’

B B’
A A’

Capacitor Resistor

P-channel MOSFET

B B’

n-channel MOSFET
Poly 1 Mask

A-A’ Section

Gate Oxide Gate Oxide

B-B’ Section
Poly 2 Mask

A A’

B B’
Poly 2 Mask

A A’

B B’
Poly 2 Mask

A-A’ Section

B-B’ Section
P-Select

A A’

B B’
P-Select

A A’

B B’
P-Select Mask – n-diffusion

A-A’ Section

n-diffusion

B-B’ Section
P-Select Mask – p-diffusion

A-A’ Section
p-diffusion

B-B’ Section
Contact Mask

A A’

B B’
Contact Mask

A A’

B B’
Contact Mask

A-A’ Section

B-B’ Section
Metal 1 Mask

A A’

B B’
Metal 1 Mask

A A’

B B’
Metal Mask

A-A’ Section

B-B’ Section
Contact Mask

A A’

B B’
Contact Mask

A A’

B B’
Contact Mask

A-A’ Section

B-B’ Section
Metal 1 Mask

A A’

B B’
Metal 1 Mask

A A’

B B’
Metal Mask

A-A’ Section

B-B’ Section

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