Fundamentals in Digital IC

Design
By

Udit Baliga- 2K12/EP/076

Vikas Yadav- 2K12/EP/083
Ekansh Rana- 2K12/EP/024
 Digital IC Design

• Integrated Circuit, sometimes called microchip, is a semiconductor wafer on which millions of tiny
resistors, capacitors and transistors are fabricated.

• Digital ICs operate only at a few well defined levels or states, rather than over a continuous range
of signal amplitudes. Their fundamental building blocks are logic gates.

• Digital IC design is to produce components such as microprocessors, FPGAs, memories

(RAM, ROM, and flash) and digital ASICs.

• Digital design focuses on logical correctness, maximizing circuit density, and placing circuits so
that clock and timing signals are routed efficiently
 Digital IC Design

• It is the goal of the IC designer to design an integrated circuit that meets a given set of
specifications while expending minimal labor and physical resources in a short time frame

• The main design parameters can be summarized in terms of:

• Performance
• Size of die
• Time to design
• Ease of verification, test generation, and testability

• Design is a continuous tradeoff to achieve adequate results for all of the above parameters
Block Diagram of a conventional IC Design Process
 Performance Considerations

• To ensure optimum performance of ICs, designers need to consider certain parameters at the logic
and circuit level.

• These parameters include:

• Power dissipation
• Delay Estimation
• Interconnects
• Reliability
• Scaling
 Power Dissipation
• Static dissipation occurs due to sub-threshold conduction, tunneling and leakage. These lead to
small amounts of current flowing through the OFF transistor. Pstatic = IstaticVDD

• Dynamic dissipation occurs primarily due to charging of the load capacitance. Pdynamic = αCVDD2f

• Total power dissipated is sum of static and dynamic dissipation components. Ptotal = Pdynamic + Pstatic

• Low power design techniques are implemented to reduce dynamic and static powers.

• Static power reduction techniques involve reducing Istatic and controlling leakage.

• Dynamic power reduction techniques include implementing small transistors, turning off portions
of clock networks where necessary, choosing a low power supply, frequency trading.
 Delay Estimation

• In digital IC designs there will be a number of paths that require attention to the timing details,
called critical paths.

• These can be recognized by using a timing analyzer, a design tool that finds the slowest path in a
logic design.

• Delays can be reduced by implementing a good microarchitecture, timing optimization at logic

level (number of stages of gates in cycle, fan-in and fan-out of gates) and timing optimization at
circuit level (transistor sizes).
 RC Delay

• The delay of logic gates is estimated as the RC product of the effective driver resistance and the
load capacitance.

• The delay of a logic gate depends on widths of transistors in the gate and capacitance of load to be
driven.

• Logic gates use minimum-length devices for least area and power consumption.
 Logical Effort

• Logical effort is the ratio of input capacitance of gate compared to input capacitance of an invertor
that can deliver the same output current.
• It indicates how much worse the gate is at producing output current as compared to an invertor.
• Logical effort is measured in simulations from delay vs. fanout plots.

Gate Type Number of Inputs

1 2 3 n
invertor 1
NAND 4/3 5/3 (n+2)/3
NOR 5/3 7/3 (2n+1)/3
XOR, XNOR 4,4 6,12
Table 1: Logical effort of common gates
 Parasitic Delay

• Parasitic delay of a gate is the delay of the gate when it drives zero load. It can be estimated with
RC delay models.

• Larger gates tend to have lower parasitic delay.

Gate Type Number of Inputs

1 2 3 n
invertor 1
NAND 2 3 n
NOR 2 3 n
multiplexer 2 4 6 2n
Table 1: Parasitic delay of common gates
 Interconnects

• The wires linking transistors together are called interconnects. (Ag, Au, Al, Ti, Cu)

• They have width w, length l, thickness t, and spacing of s from neighbors and dielectric of height h
between them and the conducting layer below.

• Interconnect increase circuit delay as wire capacitance adds loading to each gate and long wires
have significant resistance that contributes distributed RC delay or flight time.

• Capacitive coupling of wires during switching, called crosstalk, produces delay.

• Interconnect engineering is thus an integral step in digital IC designing.

 Reliability
• Designing reliable CMOS chips involves understanding and addressing the potential failure modes.

These include:
• Electromigration- It causes wearout of metal interconnects through formation of voids. High
current density leads to electron wind causing metal atoms to migrate over time.

• Self heating- High currents dissipate power in wire, raising the ambient temperature causing
increase in resistance and delay.

• Soft errors- These are random nonrecurring single bit errors in memory devices, including
SRAM, DRAM, registers and latches.

• Overvoltage failure- Tiny transistors can be destroyed by relatively low voltages. Problems
can arise from oxide breakdown, electrostatic discharge and time-dependent dielectric
breakdown of gate oxide
 Scaling
• Scaling of transistors made switching faster, lowered power dissipation and reduced cost but also
exacerbated noise and reliability issues.

• Designers need to predict the effect of size scaling on chip performance for future products.

• Transistor scaling parameters include all dimensions, device voltages and doping concentration
densities.

• Interconnect scaling includes scaling of all dimensions or keeping wire height constant.
 Structured Design Techniques
• The successful implementation of almost any IC requires attention to the details of the engineering
design process.

• Hierarchy- It involves dividing a system into modules, then repeating this process on each module
until the complexity of the submodules is at an appropriately comprehensible level of detail.

• Regularity- It involves dividing the hierarchy into a set of similar building blocks. Regularity can
exist on all levels. At circuit level, the use of uniformly sized transistors and at gate level, the use
of a finite library of fixed-height and variable-length logic gates

• Modularity- It states that modules have well-defined functions and interfaces. If modules are well
formed, the interaction with other modules can be well characterized.

• Locality- It states that other than the specified external interfaces, the internals of the module are
unimportant to the other modules. This ‘information hiding’ reduces the apparent complexity of the
module.
 Overview of Digital IC Design

• Electronic system-level design: This step creates the user functional specification. The user may
use a variety of languages and tools to create this description. These include
a C/C++ model, SystemC, SystemVerilog Transaction Level Models, Simulink and MATLAB.

• RTL design: This step converts the user specification into a register transfer level (RTL)
description. The RTL describes the exact behavior of the digital circuits on the chip, as well as the
interconnections to inputs and outputs.

• Physical design: This step takes the RTL, and a library of available logic gates, and creates a chip
design. This involves figuring out which gates to use, defining places for them, and wiring them
together.
Thank You!