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Microprocessors

Name : G.Subba Rao & B.SanthoshaKumari Designation : Lecturer Branch : Electronics & Commn. Engg. Institute : BPTC, Bapatla Subject : Microprocessors Subject Code : CM 405 Year/Semester : IV Semester Topic : Introduction & Architecture Sub -Topic : Block Diagram of 8086 Duration
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© © All Rights Reserved
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Download as PPT, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
61 views

Microprocessors

Name : G.Subba Rao & B.SanthoshaKumari Designation : Lecturer Branch : Electronics & Commn. Engg. Institute : BPTC, Bapatla Subject : Microprocessors Subject Code : CM 405 Year/Semester : IV Semester Topic : Introduction & Architecture Sub -Topic : Block Diagram of 8086 Duration
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 30

DEPARTMENT OF TECHNICAL EDUCATION

ANDHRA PRADESH
Name : G.Subba Rao & B.SanthoshaKumari
Designation : Lecturer
Branch : Electronics & Commn. Engg.
Institute : BPTC, Bapatla
Subject : Microprocessors
Subject Code : CM 405
Year/Semester : IV Semester
Topic : Introduction & Architecture
Sub -Topic : Block Diagram of 8086
Duration : 100 min.
Teaching Aids : PPT
Revised by :K.Srikanth,Lecturer,GPT,Nizamabad

9CM405.3TO4 1
Objectives

After completion of this period ,you would be able


to learn

(i) Architecture of the Intel 8086 microprocessor

(ii) Brief description of functional units of 8086

9CM405.3TO4 2
Recap

In the previous classes, you have studied about

• Basic operations of a Microprocessor based system

9CM405.3TO4 3
9CM405.3TO4 4
The functional block diagram of 8086 is divided into

• Bus Interface Unit (BIU)

• Execution Unit (EU)

9CM405.3TO4 5
• The BIU fetches instructions from memory and transfers
data between the execution unit and outside world.

• The EU decodes the instructions and executes them.

• The division of work between these two units speeds up


the processing.

9CM405.3TO4 6
Bus Interface Unit:

The blocks present in this BIU are,


•Segment Registers

•Instruction Pointer

•The Queue

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Segment Registers:

The BIU contains four 16-bit segment registers. They


are:
1. Code Segment (CS) Register

2. Stack Segment (SS) Register

3. Extra Segment (ES) Register

4. Data Segment (DS) Register

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• Each segment has a maximum capacity of 64k
bytes
• Code segment holds the base address of memory
where instructions of a program are stored
• Data segment holds the base address of memory,
where program data, variables and constants are
stored

9CM405.3TO4 9
• Stack segment holds the base address of stack, where
data related to stack operations are stored

• The ES stores the base address of memory, where data


corresponding to string operations are stored

9CM405.3TO4 10
• Each segment is assigned a base address that identifies

its lowest addressed byte storage location

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Instruction queue

• 8086 processor maintains 6-byte instruction queue

• Fetched instructions are arranged in a queue

• Operates an FIFO (first in first out )

• Output of this unit is sent to execution unit

9CM405.3TO4 12
The Execution Unit

This unit performs the following tasks,

• The EU tells the BIU where to fetch instructions or data


from

• It decodes the instructions

• Executes the instructions

9CM405.3TO4 13
For doing above tasks, the EU has following
sections,

• Execution and Control Unit


• Decoder
• ALU
• General purpose registers
• Pointer and Index registers
• Flag registers

9CM405.3TO4 14
Control Unit:
This unit directs the internal operations

Decoder:
This unit translates the instructions fetched
from memory into series of actions

ALU:
This unit performs arithmetic and logical
operations

9CM405.3TO4 15
General-purpose Registers

The 8086 has four 16-bit general purpose registers.

Each is further divided into two 8-bit registers-higher


order and lower order

They are

•Accumulator AX—AH,AL

•Base Register BX---BH,BL

•Counter Register CX---CH,CL

•Data Register DX---DH,DL


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General-purpose Registers (contd.)

• These registers are used for temporary storage of


frequently used data and intermediate results

• The advantage of storing data in the internal registers


instead of memory is that they can be accessed much
faster

9CM405.3TO4 17
Pointer and Index Registers

• There are four other general purpose registers

• Two pointer registers namely,

• Stack pointer (SP)

• Base pointer (BP)

• Two index registers namely,

• Source index (SI)

• Destination index (DI)


9CM405.3TO4 18
Pointer and Index Registers (contd.)

• These registers are used to store offset value of


memory address

• This is offset value is used in computing the


memory address

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Flag Register

• Flag register is a 16 bit register present in the Execution Unit


of 8086

• Flag register is also called as processor status register


(PSW)

• 9 of the 16 bits of a flag register are implemented

• It contains 6 status flags and 3 control flags

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Flag Register (contd.)
• Flag is a flip flop which indicate some condition produced
on the execution of an instruction or controls certain
operations of EU

• Status flags are Carry flag, Parity flag, Auxiliary Carry


flag, Zero flag, Sign flag and overflow flag

• Control flags are Trap flag, Interrupt flag and Direction


flag

9CM405.3TO4 21
Status flags
• Carry Flag (CF) :
This flag is set if there is a carry out
of the MSB in case of addition or a
borrow in case of subtraction

• Parity Flag (PF):


This flag is set if the lower byte of
the result contains even no. of 1s

• Auxiliary Carry Flag (AF):

This flag is set when there is a carry


out of the bit 3 position in an
arithmetic operation

9CM405.3TO4 22
Status flags (contd.)
• Zero Flag (ZF) :
This flag is set if the result of an
arithmetic or logical operation is zero

• Sign Flag (SF) :


It is set if an arithmetic operation
sets the MSB (negative)

• Over Flow Flag (OF):


This flag is set if an overflow occurs i.e
if the result of a signed operation is
large enough to the capacity of the
destination location ( a carry into MSB)

9CM405.3TO4 23
Control Flags

• Trap Flag (TF):


If this flag is set, the processor enters into single step execution
mode. i.e., the trap interrupt is generated after execution of each
instruction

• Interrupt Flag (IF):


If this flag is set, the external maskable interrupt is enabled.
Otherwise they are ignored

9CM405.3TO4 24
Control Flags (contd.)

• Direction Flag (DF):


This is used by String manipulation instructions. If this

flag is set, the contents of index registers will be

decremented after each operation

9CM405.3TO4 25
Summary

We have discussed about the functions of

•Segment Registers
•Instruction Pointer
•The Instruction Queue
•Execution and Control Unit
•Decoder
•ALU
•General purpose registers
•Pointer and Index registers
•Flag registers

9CM405.3TO4 26
Quiz
The length of Queue in 8086 is

a) 4-bytes

b) 6-bytes

c) 8-bytes

d) 16-bytes

9CM405.3TO4 27
Quiz (Contd.)
A segment register in 8086 holds

a) Offset address

b) Effective address

c) Base address

d) Physical address

9CM405.3TO4 28
Assignment

1. What are the functional units of 8086 ?

2. What is the function of segment register ?

3. What is the function of Queue ?

4. What is the function of Interrupt flag ?

9CM405.3TO4 29
Frequently asked questions

1. Draw the block diagram of Intel 8086

2. What are the flags of 8086 ? Explain the purpose of


each flag

9CM405.3TO4 30

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