Chapter 2

DIGITAL LOGIC FUNDAMENTALS

 Digital Logic Fundamentals

Two classes of digital logic

-- Combinatorial logic
• Inputs changed  output change to correspond
to new value
• Previous values of the inputs and outputs do not
matter
• The current outputs depend solely on the current
inputs
 Digital Logic Fundamentals

-- Sequential logic
• Outputs depend on both the current inputs and
on previous inputs and outputs
• Storage elements that record the state of the
circuit
• The same inputs may generate different outputs
and different new states, depending on the
circuit’s current state.
 Boolean algebra
• A boolean value can be either true or false;
• In digital logic, 1 is usually used to represent true.
0 to represent false.
• Boolean functions produce a boolean output
based on one or more boolean inputs.
• common functions:
AND , OR , NOT
NAND , NOR
XOR , XNOR
 Boolean algebra
-- AND Output is 1 iff every input has a value of 1
x y x^y
0 0 0
0 1 0
1 0 0
1 1 1
-- OR Output is 1 if any of its inputs is 1
x y xy
0 0 0
0 1 1
1 0 1
1 1 1
 Boolean algebra
-- NOT
a single Boolean value.
output is the complement of inputs

x x’
0 1
1 0
 Boolean algebra
-- NAND(NOT AND)
output is 1 if no inputs are not all of its inputs 1.
x y x NAND y
0 0 1
0 1 1
1 0 1
-- NOR(NOT OR)
1 1 0
output is 1 if no inputs are equal to 1.
x y x NOR y
0 0 1
0 1 0
1 0 0
1 1 1
 Boolean algebra
-- XOR(exclusive OR)
• The number of input that are 1 does matter.
• If two inputs are equal to 1,output is 0 else 1
• in general , the output is equal to 1 if an odd
number of input values are 1, and 0 if an even
number of inputs are 1.
x y x XOR y
0 0 0
0 1 1
1 0 1
1 1 0
 Boolean algebra
-- XNOR(equivalence function)
• the output is equal to 1 if an even number of
input values are 1.

x y x XNOR y
0 0 1
0 1 0
1 0 0
1 1 1
 Manipulating Boolean Functions
• DeMorgan’s Law allows a digital designer to convert
an AND function to an equivalent OR function and vice
versa. (ab)’=a’+b’
(a+b)’=a’b’
• each possible set of input values is called a minterm.
• An useful device for minimizing logic is the karnaugh
map or K-map.
Manipulating Boolean Functions

x’y’z’+x’y’z=x’y’(z+z’)=x’y’(1)=x’y’
 Multiplexers
• A multiplexer ,or MUX, is a selector.
•It chooses one of its data inputs and passes it through to
its output.

4-to-1 Mux.
 Multiplexers

With an active high enable signal.

With an active low enable signal.

 Multiplexers
• Multiplexers can be cascaded to select from a
large number of inputs.

A 4-to-1 multiplexer constructed using 2-to-1 multiplexer.

 Decoders
• A decoder as its name implies,accepts a value and
decodes it.
•It has n inputs and 2n outputs, numbered from 0 to 2n -1.

2-to-4
DEC.
 Decoders

With an active high enable signal.

With an active low enable signal.

 Encoders
• A encoder is the exact opposite of the decoder.
•It receives 2n inputs and outputs an n-bit value
corresponding to the one input that has a value of 1.

A 4-to-2 encoder.
 Encoders

With an active high enable signal.

With an active low enable signal.

 Comparators
• A comparator compares two n-bit binary values to
determine which is greater, or if they are equal.

A 1-bit comparator.
 Adders
•Adders are not only perform addition ,but also to
perform subtraction, multiplication, and division.
• Half adder inputs two 1-bit values, X and Y ,and
outputs their 2-bit sum as bits C and S.Bit C is the carry
and bit S is the sum.
 Adders
• Full adder has three inputs: the two data inputs and a
carry input C  X iYi  X i Cin  Yi Cin and S  X i  Yi  Cin .
 Adders
• With the carry input, full adders can be cascaded to
produce an n-bit adder by connecting output C of an
adder to Cin of the next adder called ripple adder.

A 4-bit ripple-adder.
 Adders
• Each full adder has a small propagation delay;these delays
add up as the carry bits are propagated.
•One solution to the delay problem is the carry lookahead
adder. The generate part ,g, g  X  Y ;The second part is the
propagate,p, p  X  Y
•In general, this can be expressed by the equation
Ci 1  g i  pi Ci

•For the 4-bit adder, these values are

C1  g 0  p0C0
C2  g1  p1C1  g1  p1 ( g 0  p0C0 )
C3  g 2  p2C2  g 2  p2 ( g1  p1 ( g 0  p0C0 ))
C4  g 3  p3C3  g 3  p3 ( g 2  p2 ( g1  p1 ( g 0  p0C0 )))
 Memory
• Memory is a group of circuits used to store data.
•A memory component has some number of memory
locations, each of which stores a binary value of some
fixed length. Ex: A memory chip 512x 8 has 512 memory
location, each has eight bits.
•The address inputs of a memory chip choose one of its
locations. Ex. The 512 x 8 memory chip has address
lines A8 A7…A0.
•The data pins on a memory chip are used to access the
data. Ex. The 512 x 8 memory chip has eight data pins
D7 D6 D0
 Memory
• Two primary classes of chips, ROM and RAM.
--ROM( Read Only Memory )
•Data is programmed into the chip
•Not change the contents of the ROM
•nonvolatile memory
•Application: lookup table and BIOS
 Memory
--RAM( Random Access Memory )
•Initially contain no data
•Store and retrieve data from these locations.
• volatile memory
•Application: temporary storage in digital circuit
and working memory in personal computers.
 BCD t0 7-segment Decoder
• The BCD to 7-segment decoder converts the binary
representation of a decimal digit,0000 to 1001.
BCD t0 7-segment Decoder

b  X 2 ' X 1 ' X 0 ' X 1 X 0 c  X 2  X 1 ' X 0

 Data Sorter
• A simple data sorter will input four 4-bit values and
output them in descending order
•The compare-and-swap module.
 Data Sorter
•The four-input data sorter.
 Sequential Components
• sequential components can retain their output values
even when their inputs change.
•The most fundamental sequential components are the
latch and flip-flop.
•The main difference :flip-flops are edge triggered and
latches are level triggered.
•The simplest type are the D latch and D flip-flop.

D flip-flop D latch
 SR latch
• SR latch,sometimes called the RS latch,has two data
inputs.
•The S input set the latch to one,and the R input reset it
to zero.
•Must ensure the S and R are never set to 1 at the same
time,or the circuit may exhibit unpredictable behavior.
 JK Flip-Flop
• Jk flip-flop resolves the problem of undefined output
associated with the SR latch.
•J=1 set the output to 1 and K=1 reset the output to 0
•JK=11 inverts the current value.
 T Flip-Flop
• T,or toggle, flip-flop
• The T input does not specify a value for this flip-flop’s
output only whether or not it should be changed.
 Sequential Components
•Flip-flops and latches may be combined in parallel to
store data with more than one bit.
•4-bit D flip-flop
 Counters
•A counter stores a binary value and, when signaled
to arithmetically increments or decrements its value.
•4-bit up counter.
 Counters
•Another variant allows the counter to count up or down.
•Any of these counters may have ability to load external
data and count to as parallel load capability.
•A 4-bit up/down counter with parallel load
 Shift Registers
•A shift register can shift its data one bit position to
the right or left.
•Several variants, shifting left ,shifting right, either
direction under external control
•4-bit left shift register
 PLA
•the Programmable Logic Array ,or PLA, contains
one or more AND-OR arrays
•The inputs and their complements are made
available to several AND gates.
•The outputs of the AND gate are then input to OR
gates, which produce the chip’s output.
 PAL
•the Programmable Array of Logic ,or PAL, is
similar to PLA but its OR block is not programmable.
•The AND inputs are programmable.
 PLD
•the Programmable Logic Device ,or PLD,
encompass PLAs and PALs and more.
• Field Programmable Gate Arrays,FPGAs, are
among the most complex PLDs available.
•FPGAs contain an array of cells, each of which can
be programmed to realize a function.
•FPGAs often contain the equivalent of 10,000 or
more simple logic gates on a single chip.