Introduction To Microprocessor & Pipelining
Introduction To Microprocessor & Pipelining
What is 214 ?
What is 24H and 1234H in binary?
Basic Computer System
𝜇P
Microprocessor Bus
Memory
Bus
Input / Output
Input / Output Device
I/O devices are used to enter programs and data as inputs and display or print the results as outputs. We are all
familiar with devices such as the keyboard, mouse, printer, monitor etc. Every form of computer system has a set
of I/O devices for human interaction.
HARD DISK
Floppy Drive
CD/DVD Drive Secondary Memory
PEN DRIVE,…
Each location is identified by its own unique address. Every location contains 1 Byte (8 bits) of data.
Microprocessor
The main function of a μP is to Fetch, Decode and Execute instructions. Instructions are a part of programs.
Firstly, μP fetches an instruction from the memory. It then decodes the instruction. This means, it “understands”
the binary pattern of the instruction, also called its opcode. Upon decoding the opcode, μP understands the
operation to be performed and hence “executes” the instruction. This entire process is called an “Instruction
cycle”.
Add CL, BL
** Of course, by advanced concepts like pipelining, multitasking, multiprocessing etc., this procedure has
become very advanced and efficient today
BUS
There are three kind of BUS:
1. Address Bus
2. Data Bus Address Data
3. Control Bus This is wrong, we will discuss later
00000H 34H
00001H 12H
Address Bus: 8086 has a 20-bit address bus, hence it can access 220
Byte memory i.e. 1MB. The address range for this memory is
00000H … FFFFFH.
FFFFFH
Data Bus: 8086 has a 16-bit data bus i.e. it can access 16 bit data in
one operation. Its ALU and internal data registers are also 16-bit.
Hence 8086 is called as a 16-bit µP.
𝑅𝐷 𝐴𝑑𝑑𝑟𝑒𝑠𝑠 > 𝐶𝑜𝑛𝑡𝑟𝑜𝑙 > 𝑑𝑎𝑡𝑎
Control Bus: The control bus carries the signals responsible for 𝑊𝑅 𝐴𝑑𝑑𝑟𝑒𝑠𝑠 > 𝐷𝑎𝑡𝑎 > 𝐶𝑜𝑛𝑡𝑟𝑜𝑙
performing various operations such as 𝑅𝐷, 𝑊𝑅 etc.
Pipelining
Pipelining is one of the biggest reason for why processor become faster and faster in every updates of
microprocessor.
8086 have two different unit (BIU and EU) that’s the reason it is possible to pipelining.
Then it come 3 stage pipelining, then 4 then 5 with parallel pipelining (supper scalar pipelining)
It have a problem when there is a brunch -> thus came brunch prediction algorithm
8086 Architecture