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The FPGA Implementation of The Digital Receiver

The document discusses the FPGA implementation of a digital receiver. It describes: 1) The digital receiver uses a polyphase filter with AD input that is decimated multiple times by a polyphase filter. 2) The polyphase filter coefficients are obtained in Matlab and implemented on FPGA using multiple delay stages and a for loop to reduce code. 3) An IFFT is used for signal detection and is realized using SFT with twiddle factors precalculated and stored on the FPGA.

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amanuel abreha
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39 views

The FPGA Implementation of The Digital Receiver

The document discusses the FPGA implementation of a digital receiver. It describes: 1) The digital receiver uses a polyphase filter with AD input that is decimated multiple times by a polyphase filter. 2) The polyphase filter coefficients are obtained in Matlab and implemented on FPGA using multiple delay stages and a for loop to reduce code. 3) An IFFT is used for signal detection and is realized using SFT with twiddle factors precalculated and stored on the FPGA.

Uploaded by

amanuel abreha
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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CEIEC

The FPGA implementation of the


digital receiver
FPGA implementation of the digital receiver CEIEC

Poly phase
 AD input N times Poly phase
decimation filter

PDW output
Parameter
code Detection

FPGA implementation of the poly-phase digital receiver


FPGA implementation of the digital receiver CEIEC

Poly phase
N times decimation
The A/D output data could be 2 or 4 times decimated.
8 times decimation can be achieved when the data received by FPGA is
processed by the decimation IP core.
After the decimation, the data stream will be recovered to original one
by order sorting .
FPGA implementation of the digital receiver CEIEC

Poly phase

 The coefficient of prototype filter is obtained in Matlab, and then


amplified and take the round figure with certain bit.
 Achieve multi-stage delay for the input signal by introducing
multiple variables.
 Introduce for loop to reduce the VHDL code editing load.
 It multiplies or divides a constant in the operation in order to
increase or decrease the parameter in order to avoid that some figure
is too large or too small. (in order to reduce the consumption of logical
resource, the constant is generally 2n such as 64, 128, etc. )
FPGA implementation of the digital receiver CEIEC

IFFT
IFFT is realized by SFT, that is, take the conjugation for the input and
output of FFT.
As the input is parallel, it is advised to adopt FFTIP core which is applied
for serial input.
Twiddle factor is calculated and saved in the FPFA register in advance.
The data with certain bit could be obtained by the amplification and
rounding.
Base 2 or base 4 structure could be applied based on the FFT points,
which can achieved in the Matlab simulation.
CEIEC

The block diagram of the digital channelization

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