PIN DIAGRAM OF 8085

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Pin Diagram of 8085

2
 Clock Signals
Pin 1 and Pin 2 (Input) and Pin 37(output)
 X1 and X2 and are clock input pins
also called as Crystal Input Pins.

 8085 can generate clock signals

internally.

 To generate clock signals internally,

8085 requires external inputs from X1
and X2.

3
 Clock signals

• Early microprocessor needed clock input to be given externally, i.e.

an extra clock generator chip is necessary.
• The clock generator chip had two pins between which a crystal or an
LC, RC circuit could be connected for the generation of basic
frequency desired.
• However, microprocessor, that were designed after 1978(Intel 8085,
M6809, etc.) had the clock generator circuit embedded in the
microprocessor chip.
• For 8085 µP crystal freq=6MHz but it reduces to 3Mhz for normal
working.
• Any µP kit would have a on chip clock generator. This internal clock
generator requires circuits like LC , RC or a crystal. The internal clock
generator divides this oscillator frequency by 2 and generates clock
signal, which can be used for µP's operation

4
 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)

 RESET IN:

◦ It is used to reset the microprocessor.

◦ It is active low signal.

◦ When the signal on this pin is low for

at least 3 clocking cycles, it forces the
microprocessor to reset itself.

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 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
 Resetting the microprocessor
means:

◦ Clearing the PC and IR.

◦ Disabling all interrupts (except TRAP).
◦ Disabling the SOD pin.
◦ All the buses (data, address, control)
are tri-stated.
◦ Gives HIGH output to RESET OUT pin.

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 RESET IN and RESET OUT
Pin 36 (Input) and Pin 3 (Output)
 RESET OUT:

◦ It is used to reset the peripheral

devices and other ICs on the circuit
when the microprocessor is reset.

◦ It is an output signal.

◦ It is an active high signal.

◦ The output on this pin goes high

whenever RESET IN is given low
signal.

◦ The output remains high as long as

RESET IN is kept low.

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 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
 SID (Serial Input Data):

o It takes 1 bit input from serial port of

8085.

o Stores the bit at the 8th position

(MSB) of the Accumulator.

o RIM (Read Interrupt Mask) instruction

is used to transfer the bit.

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 SID and SOD
Pin 4 (Input) and Pin 5 (Output)
 SOD (Serial Output Data):

o It takes 1 bit from Accumulator to

serial port of 8085.

o Takes the bit from the 8th position

(MSB) of the Accumulator.

o SIM (Set Interrupt Mask) instruction

is used to transfer the bit.

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Five Hardware Interrupts in 8085
 TRAP

 RST 7.5

 RST 6.5

 RST 5.5

 INTR

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 AD0 – AD7
Pin 19-12 (Bidirectional)
• These pins serve the dual purpose of
transmitting lower order address
and data byte.

• During 1st clock cycle, these pins act

as lower half of address.

• In remaining clock cycles, these pins

act as data bus.

• The separation of lower order

address and data is done by address
latch.
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 A8 – A15
Pin 21-28 (Unidirectional)
• These pins carry the higher order of
address bus.

• The address is sent from

microprocessor to memory.

• These 8 pins are switched to high

impedance state during HOLD and
RESET mode.

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 ALE
Pin 30 (Output)
• It is used to enable Address Latch.

• It indicates whether bus functions as

address bus or data bus.

• If ALE = 1 then
• Bus functions as address bus.

• If ALE = 0 then
• Bus functions as data bus.

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 S0 and S1
Pin 29 (Output) and Pin 33 (Output)
• S0 and S1 are called Status Pins.

• They tell the current operation

which is in progress in 8085.

S0 S1 Operation

0 0 Halt

0 1 Write

1 0 Read

1 1 Opcode Fetch

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 IO/M
Pin 34 (Output)
• This pin tells whether I/O or
memory operation is being
performed.

• If IO/M = 1 then
• I/O operation is being performed.

• If IO/M = 0 then
• Memory operation is being performed.

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 IO/M
Pin 34 (Output)
• The operation being performed is indicated by S0 and S1.

• If S0 = 0 and S1 = 1 then
• It indicates WRITE operation.

• If IO/M = 0 then
• It indicates Memory operation.

• Combining these two we get Memory Write Operation.

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 Table Showing IO/M, S0, S1 and
Corresponding Operations
Operations IO/M S0 S1
Opcode Fetch 0 1 1
Memory Read 0 1 0
Memory Write 0 0 1
I/O Read 1 1 0
I/O Write 1 0 1
Interrupt Ack. 1 1 1
Halt High Impedance 0 0

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 RD
Pin 32 (Output)
• RD stands for Read.

• It is an active low signal.

• It is a control signal used for Read

operation either from memory or
from Input device.

• A low signal indicates that data on

the data bus must be placed either
from selected memory location or
from input device.

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 WR
Pin 31 (Output)
• WR stands for Write.

• It is also active low signal.

• It is a control signal used for Write

operation either into memory or
into output device.

• A low signal indicates that data on

the data bus must be written into
selected memory location or into
output device.

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 READY
Pin 35 (Input)
• This pin is used to synchronize slower
peripheral devices with fast
microprocessor.

• A low value causes the microprocessor

to enter into wait state.

• The microprocessor remains in wait

state until the input at this pin goes
high.

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 HOLD
Pin 38 (Input)
• HOLD pin is used to request the
microprocessor for DMA transfer.

• A high signal on this pin is a request

to microprocessor to relinquish the
hold on buses.

• This request is sent by DMA

controller.

• Intel 8257 and Intel 8237 are two

DMA controllers.

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 HLDA
Pin 39 (Output)
• HLDA stands for Hold Acknowledge.

• The microprocessor uses this pin to

acknowledge the receipt of HOLD
signal.

• When HLDA signal goes high, address

bus, data bus, RD, WR, IO/M pins are
tri-stated.

• This means they are cut-off from

external environment.

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 HLDA
Pin 39 (Output)
• The control of these buses goes to
DMA Controller.

• Control remains at DMA Controller

until HOLD is held high.

• When HOLD goes low, HLDA also

goes low and the microprocessor
takes control of the buses.

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 VSS and VCC
Pin 20 (Input) and Pin 40 (Input)

• +5V power supply is connected to

VCC.

• Ground signal is connected to VSS.

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The three cycle instruction execution model

• To execute a program, the microprocessor “reads” each instruction from

memory, “interprets” it, then “executes” it.
• To use the right names for the cycles:
– The microprocessor fetches each instruction,
– decodes it,
– Then executes it.
• This sequence is continued until all instructions are performed.
• Knowing the combinations of cycles, one can calculate how long such an
instruction would require to complete.
• Knowing how many T-States an instruction requires, and keeping in mind that a
T-State is one clock cycle long, we can calculate the time using the following
formula:
Time= No. of T-States / Frequency
• For example a “MVI” instruction uses 7 T-States. Therefore, if the Microprocessor
is running at 2 MHz, the instruction would require 3.5 µSeconds to complete.

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Instruction cycle in 8085 microprocessor

• Instruction cycle is the total time to completing one instruction

execution.
• i.e. Time required to execute and fetch an entire instruction is called
instruction cycle. It consists:

• Fetch cycle – In fetch cycle, microprocessor fetches opcode from the

memory. The next instruction is fetched according to the address stored in
program counter (PC) and then stored in the instruction register.

• Decode instruction – Decoder interprets the encoded instruction from

instruction register.
• Execution cycle – The necessary steps which are carried out to get data if any
from memory and to perform the specified operation in an instruction. It
consists memory read (MR), memory write (MW), input output read (IOR)
and input output write (IOW)

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 Fetch Cycle

• The 1st byte of an instruction is its opcode, the other bytes are data
or operand’s address.
• In the beginning of fetch cycle the content of PC to the memory and
memory places the opcode on the data bus so as to transfer it to the
processor.
• The entire operation of fetching the opcode takes three clock cycles:
1. Content of pc transfer to the address bus
2. Content of memory location transfer to the data bus
3. From data bus to the IR
4. 4th cycle is for decoding the opcode
• The time required to fetch an opcode is fixed i.e. of 3 clock cycles,
and in the 4th cycles decodation occurs while the time required to
execute the instruction is depend upon the type of instruction

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 Machine cycle
• The time required by the microprocessor to complete an operation of
accessing memory or input/output devices is called machine cycle.
• The fetching, decoding and execution of a single instruction
constitutes an instruction cycle, which consists of one to five read or
write operations between processor and memory or input/output
devices. Each memory or I/O operation requires a particular time
period, called machine cycle.
• In other words, to move byte of data in or out of the microprocessor,
a machine cycle is required. Each machine cycle consists of 3 to 6
clock periods/cycles, referred to as T-states.
• Therefore we can say that, one instruction cycle consists of one to
five machine cycles and one machine cycle consists of three to six T-
states i.e. three to six clock periods,

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 Machine cycle contd.

The 8085 microprocessor has 5 basic machine cycles.

They are
1. Opcode fetch cycle (4T)
2. Memory read cycle (3 T)
3. Memory write cycle (3 T)
4. I/O read cycle (3 T)
5. I/O write cycle (3 T)
Relationships between Instruction cycle , machine
cycle and T-state

• One time period of frequency of microprocessor is called t-

state. A t-state is measured from the falling edge of one clock
pulse to the falling edge of the next clock pulse.

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 Timing Diagram of 8085
• It is the graphical representation of process in steps with respect to
time.
• The timing diagram represents the clock cycle and duration, delay,
content of address bus and data bus, type of operation i.e.
Read/write/status signals.
• The execution time is represented in T-states.
• The total amount of time taken to execute an instruction depends
upon the size of instruction and the frequency of the microprocessor.
• For e.g. consider the instruction MVI A, 02H, it is a two byte
instruction , consists of 2 machine cycles, M1 for opcode fetch and
M2 for memory read.
• M1 consists of 4 T-states and M2 consists of 3 T-states so total 7
cycles.

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Contd.

• Now in order to calculate the time we should know the frequency of

the 8085 which is 3.125 Mhz.
• So time(T) for one clock cycle is 1/3.125 = 0.32 micro seconds
• Time taken for opcode fetch is 4 * 0.32 =1.28 microseconds
• Time take for memory read/write is 3 * 0.32 = 0.96 microseconds
• Time taken for MVI A 02H is 7T i.e. 7 * 0.32 = 2.24 microseconds.

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What are the control signals used in timing
diagram of 8085 microprocessor?
1. IO/ M
IO/ M signal indicate whether I/O or memory operation is being carried out. A high on this
signal indicates I/O operation while a low indicates memory operation.
2. S0 and S1
S0 and S1 indicate the type of machine cycle in progress.
3. ALE
ALE is indicates the availability of a valid address on the multiplexed address/data lines.
When it is high act as a address bus and low act as a data bus.
4. Rd
Read is an active low signal that indicates that data is to be read form the selected
memory or i/o device through data bus.
5. WR
Write is an active low signal that indicates that data on the data bus is to be write form the
selected memory or i/o device.

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 Opcode Fetch Cycle
• The first machine cycle of every
instruction is opcode fetch cycle in
which the 8085 finds the nature of
the instruction to be executed.
• In this machine cycle, processor
places the contents of the Program
Counter on the address lines, and
through the read process, reads
the opcode of the instruction.
• The length of this cycle is varies
from 4T states to 6T states as per
the instruction.

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Opcode Fetch Cycle
• Step 1 : (State T1) In T1 state, the 8085 places the contents of program
counter on the address bus. The high-order byte of the PC is placed on
the A8-A15 lines. The low-order byte of the PC is placed on the AD0 –
AD7 lines which stays on only during T1. Thus microprocessor activates
ALE (Address Latch Enable) which is used to latch the low-order byte of
the address in external latch before it disappears.
• In T1, 8085 also sends status signals IO/M, S1, and S0. IO/M specifies
whether it is a memory or I/O operation, Si status specifies whether it
is read/write operation; S1 and S0 together indicates read, write,
opcode fetch, machine cycle operation, or whether it is in HALT state.
In opcode fetch machine cycle status signals are : IO/M = 0, S1 = 1, S0 =
1.

35
Contd.
• Step 2 : (State T2) In T2, low-order address disappears from the AD0 –
AD7 lines. (However Ao – A7remain available as they were latched
during T1). In T2, 8085 sends RD signal low to enable the addressed
memory location. The memory device then places the contents of
addressed memory location on the data bus (ADo – AD7).
• Step 3 : (State T3) During T3, 8085 loads the data from the data bus in
its Instruction Register and raises RD to high which disables the
memory device.
• Step 4 : (State T4) In T4, microprocessor decodes the opcode, and on
the basis of the instruction received, it decides whether to enter
state T5 or to enter state T1 of the next machine cycle. One byte
instructions those operate on eight bit data (8 bit operand) are
executed in T4.
• For example : MOV A, B, ANA D, ADD B, INR L, DCR C, RAL and many
more.
36
Contd.

• Step 5 : (State T5 and T6) State T5 and T6, when entered, are used for
internal microprocessor operations required by the instruction.
During T5 and T6 8085 performs stack write, internal 16 bit; and
conditional return operations depending upon the type of
instruction. One byte instructions those operate on sixteen bit data
(16 bit operand) are executed in T5 and T6. For example DCX H, PCHL,
SPHL, INX H, etc.

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 The micro RTL flow for 4-states OFMC

• OFMC: Status signals IO/M =0, S1=1, S0=1

• T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE = 1
• T2: RD = 0, (PC) = (PC) +1, AD7-AD0 M(AB)
• T3: RD = 1, , (IR) BDB
• T4: 𝜇𝑝 decodes the opcode and decides whether T5 and T6 states are
required or next machine cycle executed is T1

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Timing Diagram of Opcode fetch

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Memory READ Machine Cycle

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 Micro RTL of MRMC

• Status signals IO/M =0, S1=1, S0=0

• T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =1
• T2: RD = 0, (PC) = (PC) +1, AD7-AD0 M(AB)
• T3: RD = 1, , (Internal Reg.) AD7-AD0 or BDB

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Memory Write Cycle

42
Interrupt Acknowledge cycle for CALL instruction

• For CALL instruction, it is necessary to fetch the two bytes of the CALL
address through two additional interrupt acknowledge machine
cycles (M2 and M3 ).

• The machine cycles M4 and M5 are memory write cycles that store
the contents of the program counter on the stack, and then a new
instruction cycle begins.

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Timing Waveform for Call Instruction

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 Bus Idle Cycle

• There are few situations where the machine cycles are neither Read
nor Write.
• For execution of DAD instruction (this instruction adds the contents
of a specified register pair to the contents of HL register pair) ten T
states are required.
• This means that after execution of opcode fetch machine cycle, DAD
instruction requires 6 extra T-states to add 16 bit contents of a
specified register pair to the contents of HL register pair.
• These extra T-states which are divided into two machine cycles do
not involve any memory or I/O operation. These machine cycles are
called BUS IDLE machine cycles.
• In the case of DAD, these Bus Idle cycles are similar to memory read
cycles, except RD and ALE signals are not activated.

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Bus Idle Cycle

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 Concept of Wait States

• In some applications, speed of memory system and I/O system are

not compatible with the microprocessor’s timings.
• This means that they take longer time to read/write data. in such
situations, the microprocessor has to confirm whether a peripheral is
ready to transfer data or not.
• If READY pin is high, the peripheral is ready otherwise 8085 enters
wait state.
• Wait states continue to be inserted as long as READY is low. After the
wait state, 8085 continues with T3 of the machine cycle.
• During a wait state the contents of the address bus, the data bus, and
the control bus are all held constant.
• The wait state then gives an addressed memory or I/O port an extra
clock cycle time to output valid data on the data bus.
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Concept of Wait States

48
Timing diagram for STA 526AH

• STA means Store Accumulator -The contents of the accumulator is

stored in the specified address(526A).
• The opcode of the STA instruction is said to be 32H. It is fetched from
the memory 41FFH
• Then the lower order memory address is read(6A). - Memory Read
Machine Cycle.
• Read the higher order memory address (52).- Memory Read Machine
Cycle
• The combination of both the addresses are considered and the
content from accumulator is written in 526A. - Memory Write
Machine Cycle
• Let the content of accumulator is C7H. So, C7H from accumulator is
now stored in 526A.
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Timing Diagram of STA

50
Timing diagram for IN C0H

• Fetching the Opcode DBH from the memory 4125H.

• Read the port address C0H from 4126H.
• Read the content of port C0H and send it to the accumulator.
• Let the content of port is 5EH.

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IN C0H

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