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Chapter STA For Nanometer Designs

1. CMOS logic gates are built using NMOS and PMOS transistors, with the NMOS transistor turning on when the input is 1 and the PMOS turning off, or vice versa when the input is 0. 2. The delay of a CMOS cell depends on the output load capacitance and input transition time based on nonlinear delay models. Skew is the difference in timing between signals, while latency is the total time from a clock source to an endpoint. 3. Standard cells have pin capacitances and timing arcs specified between inputs and outputs. The delay is modeled based on output load, input transition time, and cell unateness which determines how transitions propagate through the cell.

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86 views

Chapter STA For Nanometer Designs

1. CMOS logic gates are built using NMOS and PMOS transistors, with the NMOS transistor turning on when the input is 1 and the PMOS turning off, or vice versa when the input is 0. 2. The delay of a CMOS cell depends on the output load capacitance and input transition time based on nonlinear delay models. Skew is the difference in timing between signals, while latency is the total time from a clock source to an endpoint. 3. Standard cells have pin capacitances and timing arcs specified between inputs and outputs. The delay is modeled based on output load, input transition time, and cell unateness which determines how transitions propagate through the cell.

Uploaded by

fahad ghazali1
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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STA

Chapter 2
Basics of CMOS
Channel Length
• Separation between source and drain regions
is the length of the MOS Transistor
• Smallest length is normally the feature size for
the CMOS Technology . E.g. 250 nm
CMOS logic Gate
• A CMOS logic gate is built using NMOS and
PMOS transistors
• When A =0 , NMOS is off and PMOS is on,Z =1
• When A= 1 , NMOS is on and PMOS is off, Z =0

0 on

0 1

0 off
CMOS logic Gate
• A CMOS logic gate is built using NMOS and
PMOS transistors
• When A =0 , NMOS is off and PMOS is on,Z =1
• When A= 1 , NMOS is on and PMOS is off, Z =0

1 off

1 0

1 on

• Other gates can be made which form Std. Cell


When Vg = Hi, NMOS = on
NAND Gate
A B Z NMOS on , if Vg = 1
PMOS on, if Vg = 0
0 0 1
0 1 1
1 0 1
1 1 0
NAND Gate
A B Z NMOS on , if Vg = 1 ----- NMOS off, if Vg = 0
PMOS on, if Vg = 0 ----- PMOS off, if Vg = 1
0 0 1
0 1 1
1 0 1
1 1 0
on on

1
off
0

off
0
NAND Gate
A B Z NMOS on , if Vg = 1 ----- NMOS off, if Vg = 0
PMOS on, if Vg = 0 ----- PMOS off, if Vg = 1
0 0 1
0 1 1
1 0 1
1 1 0
off on

1
on
1

off
0
NAND Gate
A B Z NMOS on , if Vg = 1 ----- NMOS off, if Vg = 0
PMOS on, if Vg = 0 ----- PMOS off, if Vg = 1
0 0 1
0 1 1
1 0 1
1 1 0
on off

1
off
0

on
1
NAND Gate
A B Z NMOS on , if Vg = 1 ----- NMOS off, if Vg = 0
PMOS on, if Vg = 0 ----- PMOS off, if Vg = 1
0 0 1
0 1 1
1 0 1
1 1 0
off off

0
on
1

on
1
CMOS logic levels

•Depending upon the specifics of the CMOS technology, there is a


small amount of leakage current that is drawn even in steady state
•Typical values for a CMOS 0.13mm inverter cell with 1.2V Vdd
supply are 0.465V for VILmax and 0.625V for VIHmin
Modeling of CMOS CELL
• Fanout of output pin of cell is the sum of
– All the input capacitances of the cells being driven
– And the sum of the capacitance of all the wire
segments
• Net plus
• Cout of driving cell
• In CMOS cell, inputs only have cap. load
Fanout
Modelling RC
Prop. delay
• Delays
– Output rise delay (Tr)
– Output fall delay (Tf)
Slew of a waveform
• Slew is typically measured in terms of the
• Transition time,
– The time it takes for a signal to transition between
two specific levels
– Inverse of slew rate
• In CMOS waveforms are asymptotic and is hard to
determine exact start and end points
• Transition time expressed thru threshold
# Falling edge thresholds:
slew_lower_threshold_pct_fall : 30.0;
slew_upper_threshold_pct_fall : 70.0;
# Rising edge thresholds:
slew_lower_threshold_pct_rise : 30.0;
slew_upper_threshold_pct_rise : 70.0;
Skew between signals & Latency
• Skew is the difference in timing between two or
more signals,
– E.g. Clock tree has 500 end points; Skew = 50ps =>
• Difference in latency between the longest path and the
shortest clock path
• Clock latency is the total time it takes from the
clock source to an
End point
Ideal Clock Source
• In the early stages, STA is with ideal CT
• Ideal clock Skew = 0ps
• Latency can be set through following options

• OR

• Uncertainty : window in which edge can occur


– Includes Jitters and timing margins
Ideal Clk source
• Jitter
– Determined by type of
clk generator
used
• set_clock_uncertainty
for additional margins
¬50 ps to compensate
for post CT effects
Timing arcs & Unateness
Standard cells

Chapter 3
Standard Cell
• A cell could be a standard cell, an IO buffer, or a
complex IP such as a USB core
• Library cell also contains desc. Unrelated to tim.
– E.g. Functionality and cell area
• Descriptions are shown using liberty syntax
Pin Capacitance
• Every input and output of a cell can specify
capacitance at the pin
– Cin is normally specified and Cout=0 in most cases

– Units normally pF , specified in the library file


Timing modeling
• Normally obtained after detailed cct. Simulation
• Delay for timing arc dependent on two factors
– Output load : Cap load @ output of inverter
– Transition time of signal @ input
• Current source based models ( offered in new lib)
• Non linear delay models: Table models
– For delay, output slew etc.
– Captures delay through the cell for various combinations
of
• Input transition time at input pin
• Total capacitance at cell output
NLDM details
• Presented in 2-D format,
– Independent variables
• Transition time and Cou
• & entries in the table denoting delay
• an input fall transition time of 0.3ns and an output load of 0.16pf will
correspond to the rise delay of the inverter of 0.0918ns
Timing Arc
• Every cell has multiple timing arc
– Combinational cells e.g. And,nand : from each i/p
to each o/p
– Sequential cells e.g. FFs : clk to output
– Data pins : with respect to clock
• Timing sense
– How o/p changes for diff. Types of i/p transitions
Unateness
• Unateness is important for timing as it specifies
how the edges (transitions) can propagate
through a cell how they appear at the output of
the cell
• Positive unate :
– Rising tr on i/p causes rising o/p (or not to change)
– Falling tr. On i/p causes falling o/p ( or not to change)
– E.g. And , A B Z or cells A B Z
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1
Unateness (cont’d)
• Negative unate
– Rising tr on i/p causes falling o/p (or not to change)
– Falling tr. On i/p causes rising o/p ( or not to change)
– E.g. Nand, nor

A B Z A B Z
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0
Unateness (Cont’d)
• Non-unate
– The o/p transition cannot be determined solely
from the direction of change of an i/p
– depends upon the state of the other inputs
– E.g. X-or
A B Z
0 0 0
0 1 1
1 0 1
1 1 0
Use of unateness

• Xor cell is used to invert polarity of a clock


• If POLCTRL =0 , DDRCLK, same pol. As MEMCLK
• If POLCTRL =1 , DDRCLK, opp. pol. As MEMCLK
Path delays
• The total delay for the logic to propagate
through a logic path
• sum of the delays through the various logic
cells and nets along the path
• Multiple paths exists
• Actual path taken depends on other i/ps
• Thus max path and min path exist b/w end pts
Max and min paths

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