Computer organization and

architecture
designing for performance

William Stallings
 CHAPTER – 3
A Top-Level View of Computer
function and Interconnection

(Unit – I)
 Introduction
 Computer components
 Computer functions
 Bus interconnection
 PCI (Peripheral Component
Interconnection)
structure
 Four main structural components
◦ CPU
◦ Main memory
◦ I/O
◦ System Interconnection
 Central
Main
processi
Memory
ng unit

System
Interconne
comput
ction
er

Input
Output
 CPU

Arithme
Register tic and
I/O s logic
unit
Syste CPU Internal
m bus CPU
interconne
Mem
ory
ction

Control
unit
 Control
Unit

Sequenti
ALU al Logic
Control
Syste CU
m bus
unit
Registers
and
Reg
Decoders

Control
Memory
Program Concept
 Hardwired systems are inflexible
 General purpose hardware can do
different tasks, given correct control
signals
 Instead of re-wiring, supply a new set of
control signals
What is a program?
 A sequence of steps
 For each step, an arithmetic or logical
operation is done
 For each operation, a different set of
control signals is needed
Function of Control Unit
 For each operation a unique code is
provided
◦ e.g. ADD, MOVE
 A hardware segment accepts the code
and issues the control signals
Computer Components
 All contemporary computer designs are
based on concepts developed by John von
Neumann and such a design is referred to
as the von Neumann architecture
 Von Neumann architecture is based on
three key concepts:
◦ Data and instructions are stored in a single
read–write memory.
◦ The contents of this memory are addressable
by location, without regard to the type of data
contained there.
◦ Execution occurs in a sequential fashion
(unless explicitly modified) from on one
instruction to the next.
 The two major components of the
system:
◦ an instruction interpreter
◦ a module of general-purpose arithmetic and
logic functions.

The above two components constitute the

CPU.
I/O components
◦ Data and instructions must be put into the
system. For this we need some sort of input
module. This module contains basic
components for accepting data and
instructions in some form and converting
them into an internal form of signals usable by
the system.
◦ A means of reporting results is needed, and
this is in the form of an output module. Taken
together, these are referred to as I/O
components.
Memory
 An input device will bring instructions and data in
sequentially.
 A program is not invariably executed sequentially; it may
jump around (e.g., the jump instruction).
 Operations on data may require access to more than
just one element at a time in a predetermined sequence.
 Thus, there must be a place to store temporarily both
instructions and data.
 That module is called memory, or main memory to
distinguish it from external storage or peripheral
devices. Von Neumann pointed out that the same
memory could be used to store both instructions and
data.
Computer Components: Top Level View
 The CPU exchanges data with memory.
 For this purpose, it typically makes use of two internal (to
the CPU) registers: a memory address register (MAR), which
specifies the address in memory for the next read or write,
and a memory buffer register (MBR), which contains the data
to be written into memory or receives the data read from
memory.
 An I/O address register (I/OAR) specifies a particular I/O
device.
 An I/O buffer (I/OBR) register is used for the exchange of
data between an I/O module and the CPU.
 A memory module consists of a set of locations, defined by
sequentially numbered addresses.
 Each location contains a binary number that can be
interpreted as either an instruction or data.
 An I/O module transfers data from external devices to CPU
and memory, and vice versa. It contains internal buffers for
temporarily holding these data until they can be sent on.
Computer function
 Execution of the program
Instruction cycle
 Processing required for a single
instruction
 Instruction cycle
 Two steps
◦ Fetch
◦ Execute
Fetch cycle execute cycle

Fetch next Execute

start halt
instruction instruction
Fetch Cycle
 Program Counter (PC) holds address of
next instruction to fetch
 Processor fetches instruction from memory
location pointed to by PC
 Increment PC
◦ Unless told otherwise
 Instruction loaded into Instruction Register
(IR)
 Processor interprets instruction and
performs required actions
Execute Cycle
 Processor-memory
◦ data transfer between CPU and main memory
 Processor I/O
◦ Data transfer between CPU and I/O module
 Data processing
◦ Some arithmetic or logical operation on data
 Control
◦ Alteration of sequence of operations
◦ e.g. jump
 Combination of above
Example of Program Execution
Example of Program Execution
Example of Program Execution
Instruction Cycle State Diagram
Interrupts
 Mechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processing

Classes of Interrrupts
 Program
◦ e.g. overflow, division by zero
 Timer
◦ Generated by internal processor timer
◦ Used in pre-emptive multi-tasking
 I/O
◦ from I/O controller
 Hardware failure
◦ e.g. memory parity error
Program Flow Control
Interrupt Cycle
 Added to instruction cycle
 Processor checks for interrupt
◦ Indicated by an interrupt signal
 If no interrupt, fetch next instruction
 If interrupt pending:
◦ Suspend execution of current program
◦ Save context
◦ Set PC to start address of interrupt handler
routine
◦ Process interrupt
◦ Restore context and continue interrupted
program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing Short I/O Wait
Program Timing Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts
 Disable interrupts
◦ Processor will ignore further interrupts whilst
processing one interrupt
◦ Interrupts remain pending and are checked after
first interrupt has been processed
◦ Interrupts handled in sequence as they occur
 Define priorities
◦ Low priority interrupts can be interrupted by
higher priority interrupts
◦ When higher priority interrupt has been
processed, processor returns to previous
interrupt
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
 Interconnection structures
 Basic types of components
◦ Processor
◦ Memory
◦ I/O
 Collection of path containing the various
modules is called interconnection
structures
Connecting
 All the units must be connected
 Different type of connection for different
type of unit
◦ Memory
◦ Input/Output
◦ CPU
Computer Modules
Memory Connection
 N words of equal length
 Word of data can be read or written on
to memory
 Receives and sends data
 Receives addresses (of locations)
 Receives control signals
◦ Read
◦ Write
◦ Timing
Input/Output Connection(1)
 Similar to memory from computer’s
viewpoint
 Output
◦ Receive data from computer
◦ Send data to peripheral
 Input
◦ Receive data from peripheral
◦ Send data to computer
Input/Output Connection(2)
 Receive control signals from computer
 Send control signals to peripherals
◦ e.g. spin disk
 Receive addresses from computer
◦ e.g. port number to identify peripheral
 Send interrupt signals (control)
CPU Connection
 Reads instruction and data
 Writes out data (after processing)
 Sends control signals to other units
 Receives (& acts on) interrupts
 The interconnection structure should
support the following types of transfers

◦ Memory to processor
◦ Processor to memory
◦ I/O to processor
◦ Processor to I/O
◦ I/O to or from memory
Buses
 There are a number of possible
interconnection systems
 Single and multiple BUS structures are
most common
 e.g. Control/Address/Data bus
 e.g. Unibus (DEC-PDP)
What is a Bus?
 A communication pathway connecting
two or more devices
 Usually broadcast
 Often grouped
◦ A number of channels in one bus
◦ e.g. 32 bit data bus is 32 separate single bit
channels
Data Bus
 Carries data
◦ Provides a path for moving data between
system modules
◦ Remember that there is no difference
between “data” and “instruction” at this level
 Width is a key determinant of
performance
◦ 8, 16, 32, 64 bit
◦ Width – no of lines(each line carry one bit)
Address bus
 Identify the source or destination of data
 e.g. CPU needs to read an instruction
(data) from a given location in memory
 Bus width determines maximum memory
capacity of system
◦ e.g. 8080 has 16 bit address bus giving 64k
address space
Control Bus
 Control and timing information
◦ Memory read/write signal
◦ Interrupt request
◦ Clock signals
 Typical control lines
◦ Memory write : causes data on the bus to be
written on to addressed location
◦ Memory read : causes data from addressed
location to be placed on the bus
◦ I/O write: causes data on the bus to be output to
the addressed I/O port
◦ I/O read : causes data from addressed I/O port to
be placed on the bus
◦ Transfer ACK: indicates that data have been
accepted from or placed on the bus
◦ Bus request: indicates that a module needs to gain
control of the bus
 Bus grant: indicates that a requesting module
has been granted control of the bus
 Interrupt request : indicates that an interrupt
is pending
 Interrupt ACK: acknowledges that the pending
interrupt has been recognized
 Clock: used to synchronise operation
 Reset : initialises all modules
Bus Interconnection Scheme
Bus
 What do buses look like?
◦ Parallel lines on circuit boards
◦ Ribbon cables
◦ Strip connectors on mother boards
 e.g. PCI
◦ Sets of wires
Operation of bus
 If one module wish to send data to another
◦ Obtain the use of bus
◦ Transfer data via the bus

 If one module wishes to request data from

another module
◦ obtain the use of bus
◦ Transfer a request to other module over the
appropriate control and address lines
◦ Wait for the second module to send data
Physical Realization of Bus
Architecture
Single Bus Problems
 Lots of devices on one bus leads to:
◦ Propagation delays
 Long data paths mean that co-ordination of bus use
can adversely affect performance
 If aggregate data transfer approaches bus capacity
 Most systems use multiple buses to
overcome these problems
Traditional (ISA) (with cache)
High Performance Bus
Elements of bus design
Bus Types
 Dedicated
◦ Separate data & address lines
 Multiplexed
◦ Shared lines
◦ Address valid or data valid control line
◦ Advantage - fewer lines
◦ Disadvantages
 More complex control
 Ultimate performance
Bus Arbitration
 More than one module controlling the
bus
 e.g. CPU and DMA controller
 Only one module may control bus at one
time
 Arbitration may be centralised or
distributed
Centralised or Distributed
Arbitration
 Centralised
◦ Single hardware device controlling bus access
 Bus Controller
 Arbiter
◦ May be part of CPU or separate
 Distributed
◦ Each module may claim the bus
◦ Control logic on all modules
Timing
 Co-ordination of events on bus
 Synchronous Timing
◦ Events determined by clock signals
◦ Control Bus includes clock line
◦ A single 1- 0 is a bus cycle (clock cycle)
◦ All devices can read clock line
◦ Usually sync on leading edge
◦ Usually a single cycle for an event
Timing
 Asynchronous Timing
◦ The occurrence of one event on a bus follows
and depends on the occurrence of a previous
event.
Synchronous Timing Diagram
Asynchronous Timing – Read
Diagram
Asynchronous Timing – Write
Diagram
PCI Bus
 Peripheral Component Interconnection
 Intel released to public domain
 32 or 64 bit
 50 lines
Typical PCI Bus Usage
PCI Bus Lines (required)
 Systems lines
◦ Including clock and reset
 Address & Data
◦ 32 time mux lines for address/data
◦ Interrupt & validate lines
 Interface Control
 Arbitration
◦ Not shared
◦ Direct connection to PCI bus arbiter
 Error lines
PCI Commands
 Transaction between initiator (master)
and target
 Master claims bus
 Determine type of transaction
◦ e.g. I/O read/write
 Address phase
 One or more data phases
PCI Read Timing Diagram
PCI Bus Arbiter
PCI Bus Arbitration