Control Units Group2
Control Units Group2
AM Malik
Control Unit
CPU is partitioned into Arithmetic Logic Unit (ALU) and
Control Unit (CU).
ADVANTAGES
DISADVANTAGES
Instruction Register
Number of Control Logic Gates,
Two Decoders
4-bit Sequence Counter
ARCHITECTURE OF HARDWIRED CONTROL UNIT
An instruction read from memory is placed in the
instruction register (IR).
The instruction register is divided into three parts: the I bit,
operation code, and address part.
First 12-bits (0-11) to specify an address, next 3-bits specify
the operation code (opcode) field of the instruction and last
left most bit specify the addressing mode I.
I = 0 for direct address
I = 1 for indirect address
ARCHITECTURE OF HARDWIRED CONTROL UNIT
For example:
Consider the case where SC is incremented to provide
timing signalsT0, T1, T 2 , T3, and T4 in sequence. At time
T4 , SC is cleared to 0 if decoder output D3 is active. This is
expressed symbolically by the statement:
D3 T4 : SC ← 0