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Unit-4 Arm Architecture

ARM is a popular reduced instruction set computing (RISC) processor architecture used in many mobile devices due to its low power consumption and reasonable performance. The first ARM processor was developed in 1978 at Cambridge University. ARM processors are now used in over 98% of mobile phones and have shipped over 10 billion units. The ARM architecture uses 32-bit registers and instructions that typically have two source registers and one destination register. Common operations include addition, subtraction, and bitwise logic.
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100% found this document useful (2 votes)
2K views

Unit-4 Arm Architecture

ARM is a popular reduced instruction set computing (RISC) processor architecture used in many mobile devices due to its low power consumption and reasonable performance. The first ARM processor was developed in 1978 at Cambridge University. ARM processors are now used in over 98% of mobile phones and have shipped over 10 billion units. The ARM architecture uses 32-bit registers and instructions that typically have two source registers and one destination register. Common operations include addition, subtraction, and bitwise logic.
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• Introduction of ARM:

• ARM stands for Advanced RISC (reduced instruction set


computer) machine. ARM started life as part of Acorn
makers of the BCC computer, and now designs chip for
apple iPad.
• The first ARM was established in Cambridge University in
1978. The Acorn group computers have developed the first
ARM commercial RISC processor in 1985. ARM was founded
and very popular in 1990.
• The ARM using more than 98% of the mobile phones in
2007 and 10 billion processors are shipped in 2008. ARM is
the latest technology which replaced by microcontroller
and microprocessors.
• Basically ARM is a 16 bit/ 32 bit Processors or Controllers.
ARM is heart of the advanced digital products like mobile
phones automotive systems digital cameras and home
networking and wireless technologies.
Why ARM is most popular:
• ARM is the most popular processors,
particularly used in portable devices due to its
low power consumption and reasonable
performance.
• ARM has got better performance when
compared to other processors. The ARM
processor is basically consisting of low power
consumption and low cost. It is very eas
• Introduction to ARM Architecture Families:
• ARM Architecture Families
• ARM Nomenclature:
• There are different versions of ARM, like ARMTDMI,
ARM10XE, the meaning of TDMI and XE is given below:
• ARM {X}{Y}{Z}{T}{D}{M}{I}{E}{J}{F}{S}
• X – Family
• Y – Memory management
• Z – Cache
• T – THUMB 16-bit decoder
• D – JTAG Debug
• M – Fast multiplier
• I – Embedded ICE macro cell
• E – Enhanced Instruction
• J – Jazelle (Java)
• F – Vector floating point unit
• S – Synthesizable version
• Data items are placed in the register file—a storage bank made up of 32-bit
registers. Since the ARM core is a 32-bit processor, most instructions treat
the registers as holding signed or unsigned 32-bit values.
• The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-
bit values as they are read from memory and placed in a register.
• ARM instructions typically have two source registers, Rn and Rm, and a
single result or destination register, Rd. Source operands are read from the
register file using the internal buses A and B, respectively.
• The ALU (arithmetic logic unit) or MAC (multiply-accumulate unit) takes the
register values Rn and Rm from the A and B buses and computes a result.
Data processing instructions write the result in Rd directly to the register file.
Load and store instructions use the ALU to generate an address to be held in
the address register and broadcast on the Address bus.
• One important feature of the ARM is that register Rm alternatively can be
preprocessed in the barrel shifter before it enters the ALU. Together the
barrel shifter and ALU can calculate a wide range of expressions and
addresses.
• After passing through the functional units, the result in Rd is written back to
the register file using the Result bus.
• For load and store instructions the incrementer updates the address register
before the core reads or writes the next register value from or to the next
sequential memory location.
• The processor continues executing instructions until an exception or
interrupt changes the normal execution flow.
Register organisation
How to Read Assembly Instructions: Mnemonics and Operands
• Every instruction begins with a mnemonic that represents an operation.
Following the mnemonic are the operands that will be operated on. These
are typically destination and source operands, as seen below.

MNEMONIC DEST, SRC1, SRC2

• The ADD adds R2 to R1 and puts the result in register R0 This is the
typical way to read an assembly instruction. Add R2 to R1 and put it (the
result) in R0. The equivalent machine code that will execute on the
processor is shown alongside the ADD instruction.
• The 'Cond' field contains '1110' for always execute. These bits come into
play when using conditional suffixes appended to the ADD operation.
The next field is unused and set to zero. The 'I' field is zero because 'Op2'
is a register and not an immediate value. The 'S' field is zero because we
did not append an S to the ADD operation, i.e., we don't want this
instruction to update the status register flags (N, Z, C, and V, discussed
above).

Cond I OpCd S Rn Rd Op2


ADD R0, R1, R2
Condition suffixes
interrupts

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