ASIC DESIGN

RK PRASAD
ASSISTANT PROFESSOR
DEPARTMENT OF ECE
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• Types of ASICs – Design flow – Economics of
ASICs – ASIC cell libraries – CMOS logic cell data
path logic cells – I/O cells – cell compilers.
• ASIC Library design: Transistors as resistors –
parasitic capacitance – logical effort
• programmable ASIC design software: Design
system – logic synthesis – half gate ASIC.
• Low level design entry: Schematic entry – low
level design languages – PLA tools – EDIF – An
overview of VHDL and verilog. Logic synthesis in
verilog and & VHDL simulation.

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 BOOKS
TEXT BOOKS
1.Application specific Integrated Circuits”, J.S. Smith, Addison
Wesley.
2. Principles of CMOS VLSI Design : A System Perspective, N. Westle & K.
Eshraghian ,Addison– Wesley Pub.Co.1985.
REFERENCES
1.Basic VLSI Design :Systems and Circuits, Douglas A. Pucknell &
Kamran Eshraghian,Prentice Hall of India Private Ltd. , New Delhi ,
1989.
2.Introduction to VLSI System,C. Mead & L. Canway, Addison
Wesley Pub
3.Introduction to NMOS & VLSI System Design, A. Mukharjee,
Prentice Hall,
4.The Design & Analysis of VLSI Circuits, L. A. Glassey & D. W.
Dobbepahl, Addison Wesley
Pub Co. 1985.
5.Digital Integrated Circuits: A Design Perspective, Jan A. Rabey, Prentice
Hall of India Pvt Ltd

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 INTRODUCTION

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 ASIC - INTRODUCTION
• An ASIC (pronounced “a-sick”; bold typeface
defines a new term) is an application-specific
integrated circuit
 In Integrated Circuit (IC) designed to perform a specific
function for a specific application
 As opposed to a standard, general purpose off-the-
shelf part such as a commercial microprocessor or a
7400 series IC
 Gate equivalent - a unit of size measurement
corresponding to a 4 transistor gate equivalent (e.g. a 2
input NOR gate)
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• As the name indicates, ASIC is a non-standard
integrated circuit that is designed for a specific
use or application.
• Generally an ASIC design will be undertaken for
a product that will have a large production run ,
and the ASIC may contain a very large part of the
electronics needed on a single integrated circuit.
• Examples for ASIC Ics are : a chip for a toy
bear that talks; a chip for a satellite; a chip
designed to handle the interface between memory
and a microprocessor for a workstation CPU; and
a chip containing a microprocessor as a cell
together with other logic.

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 ASIC vs Standard IC
 Standard ICs – ICs sold as Standard Parts
 SSI/LSI/ MSI IC such as MUX, Encoder, Memory Chips, or
Microprocessor IC
 Application Specific Integrated Circuits (ASIC) – A Chip
for Toy Bear, Auto-Mobile Control Chip, Different Communication Chips [
GRoT: ICs not Found in Data Book]
 Concept Started in 1980s
 An IC Customized to a Particular System or Application –
Custom ICs
 Digital Designs Became a Matter of Placing of Fewer CICs or ASICs
plus Some Glue Logic
 Reduced Cost and Improved Reliability
 Application Specific Standard Parts (ASSP) – Controller Chip
for PC or a Modem

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Levels of integration
 SSI - Small scale integration
 100 transistors per cubic centimeter
 MSI - Medium scale integration
 1000 transistors per cubic centimeter
 increased the range of integrated logic available to counters and similar,
larger scale, logic functions
 LSI - Large scale integration
10000 transistors per cubic centimeter
packed even larger logic functions, such as the first microprocessors, into a
single chip
 VLSI - Very large scale integration
1 million transistors per cubic centimeter
offers 64-bit microprocessors, complete with cache memory and floating-
point arithmetic units—well over a million transistors—on a single piece of
silicon
 USLI - Ultra large scale integration
1 Billion transistors per cubic centimeter
All advanced systems

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Implementation technology
– TTL –Transistor Transistor technology

– ECL – Emitter Coupled Logic

– MOS - NMOS, CMOS –

Metal oxide semiconductor transistor logic

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 An Integrated Circuit

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 Types of ASICs

Full-Custom ASICs: Possibly all logic cells and all mask layers customized

Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
Types of ASICs
 Full-Custom ICs/Fixed ASICs and Programmable ASICs
 Wafer : A circular piece of pure silicon (10-15 cm in dia, but
wafers of 30 cm dia are expected soon-IEEE micro-
Sep/Oct. 1999, pp 34-43)
 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of
chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one IC
design
 Mask Layers: Each IC is manufactured with successive
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen or so define Interconnect

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 Types of ASICs – Cont’d
• Full-Custom ASICs
• Standard-Cell–Based ASICs
• Gate-Array–Based ASICs
• Channeled Gate Array
• Channel Less Gate Array
• Structured Gate Array
• Programmable Logic Devices
• Field-Programmable Gate Arrays
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 Types of ASICs – Cont’d
Full-Custom ASICs
 Include some (possibly all) customized logic cells
 Have all their mask layers customized
 Full-custom ASIC design makes sense only
 When no suitable existing libraries exist
 Existing library cells are not fast enough
 The available pre-designed/pre-tested cells consume too much
power that a design can allow
 The available logic cells are not compact enough to fit
 ASIC technology is new or/and so special that no cell library exits.
 Offer highest performance and lowest cost (smallest die
size) but at the expense of increased design time, complexity,
higher design cost and higher risk.
 Some Examples: High-Voltage Automobile Control Chips, Ana-Digi
Communication Chips, Sensors and Actuators
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 Full-Custom ASICs(HAND HELD)
• All mask layers are customized in a full-custom
ASIC
– Generally, the designer lays out all cells by hand
– Some automatic placement and routing may be done
– Critical (timing) paths are usually laid out completely by
hand
• Full-custom design offers the highest performance
and lowest part cost (smallest die size) for a given
design
• The disadvantages of full-custom design include
increased design time, complexity, design expense,
and highest risk

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 Full-Custom ASICs(HAND HELD) Contd….
• Microprocessors (strategic silicon) were
exclusively full-custom, but designers are
increasingly turning to semicustom ASIC
techniques in this area as well
• Other examples of full-custom ICs or ASICs are
requirements for high-voltage (automobile),
analog/digital (communications), sensors and
actuators, and memory (DRAM)

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 Standard-Cell-Based ASICs
• A cell-based ASIC ( CBIC —“sea-
bick”)
• Standard cells
• Possibly mega cells , mega
functions , full-custom blocks ,
system-level macros( SLMs ), fixed
blocks , cores , or Functional
Standard Blocks ( FSBs )
• All mask layers are customized -
transistors and interconnect
– Automated buffer sizing,
placement and routing
• Custom blocks can be embedded
• Manufacturing lead time is about
eight weeks.

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Standard Cell Layout

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Standard Cell ASIC Routing
 A “wall” of standard cells forms a flexible block
 Metal2 may be used in a feedthrough cell to cross over cell rows
that use metal1 for wiring
 Other wiring cells: spacer cells , row-end cells , and power cells

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Gate-Array-Based ASICs
• In a gate-array-based ASIC, the transistors are
predefined on the silicon wafer
• The predefined pattern of transistors is called
the base array
• The smallest element that is replicated to
make the base array is called the base or
primitive cell
• The top level interconnect between the
transistors is defined by the designer in custom
masks - Masked Gate Array (MGA)

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Design is performed by connecting
predesigned and characterized logic cells
from a library (macros)
After validation, automatic placement and
routing are typically used to convert the
macro-based design into a layout on the
ASIC using primitive cells
Types of MGAs:
 Channeled Gate Array
 Channelless Gate Array
 Structured Gate Array
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Gate-Array-Based ASICs
 Channeled Gate Array
 Only the interconnect is customized

 The interconnect uses predefined spaces

between rows of base cells
 Manufacturing lead time is between two
days and two weeks

 Channel less Gate Array

 There are no predefined areas set aside
for routing - routing is over the top of the
gate-array devices
 Achievable logic density is higher than
for channeled gate arrays
 Manufacturing lead time is between two
days and two weeks

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Gate-Array-Based ASICs (cont.)
 Structured Gate Array
 Only the interconnect is customized

 Custom blocks (the same for each design) can be embedded

 These can be complete blocks such as a processor or memory
array, or An array of different base cells better suited to
implementing a specific function
 Manufacturing lead time is between two days and two weeks.

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Semi-Custom ASICs
• ASICs , for which all of the logic cells are
predesigned and some (possibly all) of the
mask layers are customized are called semi
custom ASICs.
• Using the predesigned cells from a cell library
makes the design , much easier.
• There are two types of semicustom ASICs
• (i) Standard-cell–based ASICs (ii)Gate-array–
based ASICs.
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Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
 PLDs - PLDs are low-density
devices which contain 1k – 10 k
gates and are available both in
bipolar and CMOS technologies
[PLA, PAL or GAL]
 CPLDs or FPLDs or
FPGAs - FPGAs combine
architecture of gate arrays with
programmability of PLDs.
User Configurable
 Contain Regular Structures
- circuit elements such as
AND, OR, NAND/NOR gates,
FFs, Mux, RAMs,
Allow Different
Programming Technologies
 Allow both Matrix and
Row-based Architectures
25
Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA

26
 Programmable Logic Devices
 No customized mask layers or logic cells
 Fast design turnaround
 A single large block of programmable interconnect
 Erasable PLD (EPLD)
 Mask-programmed PLD
 A matrix of logic macro cells that usually consist of
programmable array logic followed by a flip-flop or latch

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 Field Programmable Gate Array
 None of the mask layers are customized
 A method for programming the basic logic cells and the
interconnect
 The core is a regular array of programmable basic logic cells
that can implement combinational as well as sequential logic
(flip-flops)
 A matrix of programmable interconnect surrounds the basic
logic cells
 Programmable I/O cells surround the core
 Design turnaround is a few hours

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Why FPGA-based ASIC Design?
 Choice is based on Many Factors
;
 Speed
 Gate Density
Requirement FPGA/FPLD Discrete Logic Custom Logic

Speed

 Development Time Gate Density

 Prototyping and Cost

Simulation Time
 Manufacturing Lead Time
Development Time

 Future Modifications Prototyping and Sim.

 Inventory Risk Manufacturing

 Cost Future Modification

Inventory

Development Tools

Very Effective Adequate Poor

29
Design Flow A design flow is a sequence of steps to design an
ASIC
• 1. Design entry. Using a hardware description language
(HDL) or schematic entry.
• 2. Logic synthesis. Produces a netlist—logic cells and their
connections.
• 3. System partitioning. Divide a large system into ASIC-sized
pieces. 4. Prelayout simulation. Check to see if the design
functions correctly.
• 5. Floorplanning. Arrange the blocks of the netlist on the
chip.
• 6. Placement. Decide the locations of cells in a block.
• 7. Routing. Make the connections between cells and blocks.
• 8. Extraction. Determine the resistance and capacitance of
the interconnect.
• 9. Postlayout simulation. Check to see the design still works
with the added loads of the interconnect.
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 Design Flow
1. Design entry - Using a hardware
description language ( HDL ) or
schematic entry
2. Logic synthesis - Produces a
netlist - logic cells and their
connections
3. System partitioning - Divide a
large system into ASIC-sized
pieces
4. Prelayout simulation - Check to
see if the design functions
correctly
5. Floorplanning - Arrange the
blocks of the netlist on the chip
6. Placement - Decide the
locations of cells in a block
7. Routing - Make the connections
between cells and blocks
8. Extraction - Determine the
resistance and capacitance of
the interconnect
9. Postlayout simulation - Check
to see the design still works with
the added loads of the
interconnect
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 ASIC Cell Libraries
• The cell library is the key part of ASIC design.
• For a programmable ASIC the FPGA company
supplies you with a library of logic cells in the
form of a design kit
• For MGAs and CBICs you have three choices:
• 1. ASIC vendor (the company that will build your
ASIC) will supply a cell library
• 2.You can buy a cell library from a third-
party library vendor
• 3. You can build your own cell library

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• The first choice, using an ASIC-vendor library ,
requires you to use a set of design tools approved
by the ASIC vendor to enter and simulate your
design.
• An ASIC vendor library is normally a phantom
library —the cells are empty boxes, or phantoms ,
but contain enough information for layout.
• After you complete layout you hand off a netlist
to the ASIC vendor, who fills in the empty boxes
( phantom instantiation ) before manufacturing
your chip.

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• The second and third choices require you to make a buy-or-
build decision . If you complete an ASIC design using a cell
library that you bought, you also own the masks
(the tooling ) that are used to manufacture your ASIC.
• This is called customer-owned tooling ( COT , pronounced
“see-oh-tee”).
• The third choice is to develop a cell library in-house. Many
large computer and electronics companies make this
choice.
• Most of the cell libraries designed today are still developed
in-house despite the fact that the process of library
development is complex and very expensive.

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• However created, each cell in an ASIC cell library must
contain the following:
• A physical layout
• A behavioral model
• A Verilog/VHDL model
• A detailed timing model
• A test strategy
• A circuit schematic
• A cell icon
• A wire-load model
• A routing mode

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 Requirements for ASIC Designers
• needs a high-level, behavioral model for each cell
• a detailed timing model for each cell to
determine the performance of the critical pieces
of an ASIC
• All ASICs need to be production tested
• If the ASIC designer uses schematic entry, each
cell needs a cell icon together with connector and
naming information that can be used by design
tools from different vendors
• Lookup table known as wire bond table to
calculate the parasitic capacitance.
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Data path Logic Cells
Suppose we wish to build an n -bit adder (that adds two n -bit
numbers) and to exploit the regularity of this function in the
layout. We can do so using a data path structure.
The following two functions, SUM and COUT, implement the sum
and carry out for a full adder ( FA ) with two data inputs (A, B)
and a carry in, CIN:
SUM = A ⊕ B ⊕ CIN = SUM(A, B, CIN) = PARITY(A, B, CIN)
COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN).
The sum uses the parity function ('1' if there are an odd numbers
of '1's in the inputs).
The carry out, COUT, uses the 2-of-3 majority function ('1' if the
majority of the inputs are '1').
We can combine these two functions in a single FA logic cell,
ADD(A[ i ], B[ i ], CIN, S[ i ], COUT),
 S[ i ] = SUM (A[ i ], B[ i ], CIN)
COUT = MAJ (A[ i ], B[ i ], CIN)
Now we can build a 4-bit ripple-carry adder ( RCA ) by
connecting four of these ADD cells together as shown in
Figure (b).
The i th ADD cell is arranged with the following: two bus
inputs A[ i ], B[ i ]; one bus output S[ i ]; an input, CIN,
that is the carry in from stage ( i – 1) below and is also
passed up to the cell above as an output; and an output,
COUT, that is the carry out to stage ( i + 1) above.
In the 4-bit adder shown in Fig.we connect the carry
input, CIN[0], to VSS and use COUT[3] and COUT[2] to
indicate arithmetic overflow
Notice that we build the ADD cell so that COUT[2] is
available at the top of the data path when we need it.
(a) A full-adder (FA) cell with inputs (A and B), a carry in, CIN, sum output, S, and
carry out, COUT. (b) A 4-bit adder. (c) The layout, using two-level metal, with
data in m1 and control in m2. In this example the wiring is completed outside
the cell; it is also possible to design the datapath cells to contain the wiring.
Using three levels of metal, it is possible to wire over the top of the datapath
cells. (d) The datapath layout.
Figure (c) shows a layout of the ADD cell. The A inputs, B
inputs, and S outputs all use m1 interconnect running in the
horizontal direction—we call these data signals.
Other signals can enter or exit from the top or bottom and
run vertically across the datapath in m2—we call
these control signals.
We can also use m1 for control and m2 for data, but we
normally do not mix these approaches in the same
structure. Control signals are typically clocks and other
signals common to elements.
Figure (c) the carry signals, CIN and COUT, run vertically in
m2 between cells..
 To build a 4-bit adder we stack four ADD cells creating the
array structure shown in Figure (d). In this case the A and B
data bus inputs enter from the left and bus S, the sum, exits at
the right, but we can connect A, B, and S to either side if we
want
The layout of buswide logic that operates on data signals in this
fashion is called a datapath. The module ADD is a datapath
cell or datapath element .
Just as we do for standard cells we make all the datapath cells
in a library the same height so we can abut other datapath cells
on either side of the adder to create a more complex datapath
What is the difference between using a data-path,
standard cells, or gate arrays?
 Cells are placed together in rows on a CBIC or an MGA, but
there is no generally no regularity to the arrangement of the
cells within the rows we let software arrange the cells and
complete the interconnect

Datapath layout automatically takes care of most of the

interconnect between the cells with the following advantages:
• Regular layout produces predictable and equal delay for each
bit.
Interconnect between cells can be built into each cell.
• There are some disadvantages of using a datapath:
The overhead (buffering and routing the control signals, for example)
can make a narrow (small number of bits) datapath larger and slower
than a standard-cell (or even gate-array) implementation.
Datapath cells have to be predesigned (otherwise we are using full-
custom design) for use in a wide range of datapath sizes. Datapath cell
design can be harder than designing gate-array macros or standard
cells.
Software to assemble a datapath is more complex and not as widely
used as software for assembling standard cells or gate arrays.
There are some newer standard-cell and gate-array tools that can take
advantage of regularity in a design and position cells carefully. The
problem is in finding the regularity if it is not specified. Using a
datapath is one way to specify regularity to ASIC design tools.
 DATA PATH ELEMENTS
some typical data path symbols for an adder , use heavy lines (they
are 1.5 point wide) with a stroke to denote a data bus (that flows in
the horizontal direction in a data path), and regular lines (0.5 point) to
denote the control signals (that flow vertically in a data path).
At the risk of adding confusion where there is none, this stroke to
indicate a data bus has nothing to do with mixed-logic conventions.
For a bus, A[31:0] denotes a 32-bit bus with A[31] as the leftmost
or most-significant bit or MSB , and A[0] as the least-significant
bit or LSB.
Sometimes we shall use A[MSB] or A[LSB] to refer to these bits.
Notice that if we have an n -bit bus and LSB = 0, then MSB = n – 1.
Also, for example, A[4] is the fifth bit on the bus (from the LSB). We
use a ' S ' or 'ADD' inside the symbol to denote an adder instead of '+',
so we can attach '–' or '+/–' to the inputs for a subtractor or
adder/subtractor.
Symbols for a datapath adder. (a) A data bus is shown
by a heavy line (1.5 point) and a bus symbol. If the bus
is n -bits wide then MSB = n – 1. (b) An alternative
symbol for an adder. (c) Control signals are shown as
lightweight (0.5 point) lines.

We may need to explicitly tie CIN[0] to VSS and use

COUT[MSB] and COUT[MSB – 1] to detect overflow
 Adders
We can view addition in terms of generate , G[ i ], and propagate ,
P[ i ], signals.

method 1 method 2

G[i] = A[i] · B[i] G[ i ] = A[ i ] · B[ i ]

P[ i ] = A[ i ]  B[ i P[ i ] = A[ i ] + B[ i ]

C[ i ] = G[ i ] + P[ i ] · C[ i ] = G[ i ] + P[ i ] ·
C[ i –1] C[ i –1]

S[ i ] =
S[ i ] = P[ i ]  C[ i –1]
A[ i ]  B[ i ]  C[ i –1]
where C[ i ] is the carry-out signal from stage i , equal to
the carry in of stage ( i + 1).
Thus, C[ i ] = COUT[ i ] = CIN[ i + 1].
We need to be careful because C[0] might represent
either the carry in or the carry out of the LSB stage.
For an adder we set the carry in to the first stage (stage
zero), C[–1] or CIN[0], to '0'.
Some people use delete (D) or kill (K) in various ways for
the complements of G[i] and P[i], but unfortunately
others use C for COUT and D for CIN—so I avoid using
any of these.
 Transistors as Resistors
In “CMOS Transistors,” we modeled transistors using ideal switches.
If this model were accurate, logic cells would have no delay.

.
A model for CMOS logic delay. (a) A CMOS inverter with a load capacitance, C out
b.Input, v(in1) , and output,v(out1) , waveforms showing the definition of the
falling propagation delay, t PDf .
The model predicts t PDf ª R pd ( C p + C out ).
C.The model for the inverter includes: the input capacitance, C ; the pull-up
resistance ( R pu ) and pull-down resistance ( R pd ); and the parasitic output
capacitance, C p .
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The ramp input, v(in1) , to the inverter in Figure (a) rises quickly
from zero to V DD . In response the output, v(out1) , falls
from V DD to zero.
In Figure (b) we measure the propagation delay of the
inverter, t PD , using an input trip point of 0.5 and output trip points
of 0.35 (falling, t PDf ) and 0.65 (rising, t PDr ).
Initially the n -channel transistor, m1 , is off .
As the input rises, m1 turns on in the saturation region
( V DS > V GS – V t n ) before entering the linear region ( V DS < V GS –
V t n ). We model transistor m1 with a resistor, R pd (Figure 3.1 c);
this is the pull-down resistance .
The equivalent resistance ofm2 is the pull-up resistance , R pu .
Delay is created by the pull-up and pull-down
resistances, R pd and R pu , together with the parasitic capacitance
at the output of the cell, C p (the intrinsic output capacitance )
and the load capacitance (or extrinsic output capacitance ), C out
If we assume a constant value for R pd , the output reaches a lower
trip point of 0.35
The expression for the rising delay (with a 0.65 output trip point)
is identical in form.
Delay thus increases linearly with the load capacitance.
We often measure load capacitance in terms of a standard load

These intrinsic parasitic capacitance values depend on the choice

of output trip points, even though C pf R pdf and C pr R pdr are
constant for a given input trip point and waveform, because the
pull-up and pull-down resistances depend on the choice of
output trip points.
 Transistor Parasitic Capacitance

 Logic-cell delay results from transistor resistance, transistor

(intrinsic) parasitic capacitance, and load (extrinsic) capacitance.
When one logic cell drives another, the parasitic input
capacitance of the driven cell becomes the load capacitance of
the driving cell and this will determine the delay of the driving
cell.
 The Parasitic Capacitance depends upon
 1. Junction Capacitance
 2.Overlap Capacitance
 3.Gate Capacitance
 4.Input Slew Rate
(a) An n -channel MOS transistor with (drawn) gate length L and width W.
(b) The gate capacitance is split into: the constant overlap
capacitances C GSOV , C GDOV , and C GBOV and the variable
capacitances CGS , C GB , and C GD , which depend on the operating
region.

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 (c) A view showing how the different capacitances are approximated
by planar components ( T FOX is the field-oxide thickness).
(d) C BS and C BD are the sum of the area ( C BSJ , CBDJ ), sidewall
( C BSSW , C BDSW ), and channel edge ( C BSJ GATE , C BDJ GATE )
capacitances.

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(e)–(f) The dimensions of the gate, overlap, and sidewall
capacitances (L D is the lateral diffusion).

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Junction Capacitance
• Junction capacitances, CBD and CBS, consist of two parts: junction area
and sidewall

• Both CBD and CBS have different physical characteristics with parameters:
CJ and MJ for the junction, CJSW and MJSW for the sidewall, and PB is
Common

• CBD and CBS depend on the voltage across the junction (VDB and VSB)

• The sidewalls facing the channel (CBSJGATE and CBDJGATE) are different
from the side- walls that face the field

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 Overlap Capacitance
• The overlap capacitance calculations for CGSOV and CGDOV account for lateral
diffusion
Gate Capacitance
• The gate capacitance depends on the operating region
• The gate–source capacitance CGS varies from zero (off) to 0.5CO in the
linear region to (2/3)C O in the saturation region
• The gate–drain capacitance CGD varies from zero (off) to 0.5CO
(linear region) and back to zero (saturation region)
• The gate–bulk capacitance CGB is two capacitors in series: the fixed
gate-oxide capaci- tance, CO, and the variable depletion capacitance,
CS
• As the transistor turns on the channel shields the bulk from the gate
and CGB falls to zero
• Even with VGS =0V, the depletion width under the gate is finite and thus
CGB is less than CO
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Input Slew Rate

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 Logical Effort
Logical effort is a term coined by Ivan Sutherland and Robert
Sproull [1991], that has as its basis the time-constant analysis of
Carver Mead, Chuck Seitz, and others.
We add a “catch all” non-ideal component of delay, t q , to
t PD = R ( C out + C p )
that includes: (1) delay due to internal parasitic capacitance;
(2) the time for the input to reach the switching threshold of the
cell;
(3) the dependence of the delay on the slew rate of the input
waveform.
With these assumptions we can express the delay as follows:
t PD = R ( C out + C p ) + t q .
 We will use a standard-cell library for a 3.3 V, 0.5 m m (0.6 m m
drawn) technology (from Compass) to illustrate our model. We
call this technology C5 ; it is almost identical to the G5 process
The equation for the delay of a 1X drive, two-input NAND cell is in
the form of
t PD = (0.07 + 1.46 C out + 0.15) ns
 The delay due to the intrinsic output capacitance (0.07 ns,
equal to RC p ) and the non-ideal delay ( t q = 0.15 ns) are
specified separately.
 The non-ideal delay is a considerable fraction of the total
delay, so we may hardly ignore it
 The data book tells us the input trip point is 0.5 and the output
trip points are 0.35 and 0.65. We can use above Eq. to
estimate the pull resistance for this cell as R ª 1.46 nspF –1 or
about 1.5 k W .
 The above equation is for the falling delay
We can scale any logic cell by a scaling factor s (transistor gates
become s times wider, but the gate lengths stay the same), and as a
result the pull resistance ‘R’ will decrease to ’R / s’ and the parasitic
capacitance C p will increase to sC p .
Since t q is non-ideal, by definition it is hard to predict how it will
scale.
We shall assume that t q scales linearly with s for all cells.
The total cell delay then scales as follows:
t PD = ( R / s )·( C out + sC p ) + st q
For example, the delay equation for a 2X drive ( s = 2), two-input
NAND cell is
t PD = (0.03 + 0.75 C out + 0.51) ns
Compared to the 1X version , the output parasitic delay has
decreased to 0.03 ns (from 0.07 ns)
The pull resistance has decreased by a factor of 2 from 1.5 k W to
0.75 k W , as we would expect; and the non-ideal delay has
increased to 0.51 ns (from 0.15 ns).
 The differences between our predictions and the actual values
give us a measure of the model accuracy.
We rewrite above equation using the input capacitance of the
scaled logic cell, C in = s C ,

Finally we normalize the delay using the time constant formed

from the pull resistance R inv and the input capacitance C inv of a
minimum-size inverter:
The time constant Tau ,

is a basic property of any CMOS technology. We shall measure

delays in terms of t .
The delay equation for a 1X (minimum-size) inverter in the C5
library is
Thus tq inv = 0.1 ns and R inv = 1.60 k W .
The input capacitance of the 1X inverter (the standard load for this
library) is specified in the data book as C inv =0.036 pF;
thus t = (0.036 pF)(1.60 k W ) = 0.06 ns for the C5 technology.
The use of logical effort consists of rearranging and understanding
the meaning of the various terms in above Eq.
The delay equation is the sum of three terms,
d=f+p+q
We give these terms special names as follows:
 delay = effort delay + parasitic delay + non-ideal delay
 The effort delay f we write as a product of logical effort, g , and
electrical effort, h: f = gh .
 So we can further partition delay into the following terms
delay = logical effort ¥ electrical effort + parasitic delay + nonideal
delay
The logical effort g is a function of the type of logic cell
g = RC/ τ
The electrical effort h depends only on the load
capacitance C out connected to the output of the logic cell and the
input capacitance of the logic cell, C in ; thus
h = C out / C in
The parasitic delay p depends on the intrinsic parasitic
capacitance C p of the logic cell, so that
p = RC p / τ
Library-Cell Design
 The optimum cell layout for each process generation
changes because the design rules for each ASIC vendor’s
process are always slightly different—even for the same
generation of technology.
 If a cell library is to be used with both processes, we could
construct the library by adopting the most stringent rules
from each process.
 A library constructed in this fashion may not be
competitive with one that is constructed specifically for
each process.
 Even though ASIC vendors prize their design rules as
secret, it turns out that they are similar—except for a few
details. Unfortunately, it is the details that stop us moving
designs from one process to another.
 Unless we are a very large customer it is difficult to
have an ASIC vendor change or waive design rules for
us.
 We would like all vendors to agree on a common set of
design rules.
 This is, in fact, easier than it sounds. The reason that
most vendors have similar rules is because most
vendors use the same manufacturing equipment and a
similar process.
 It is possible to construct a highest common
denominator library that extracts the most from the
current manufacturing capability.
 Some library companies and the large Japanese ASIC
vendors are adopting this approach.
 Layout of library cells is either hand-crafted or uses some form
of symbolic layout .
 Symbolic layout is usually performed in one of two ways:
using either interactive graphics or a text layout language.
 Shapes are represented by simple lines or rectangles, known
as sticks or logs , in symbolic layout.
 The actual dimensions of the sticks or logs are determined after
layout is completed in a post-processing step.
 An alternative to graphical symbolic layout uses a text layout
language, similar to a programming language such as C, that directs
a program to assemble layout.
 The spacing and dimensions of the layout shapes are defined in
terms of variables rather than constants.
 These variables can be changed after symbolic layout is complete
to adjust the layout spacing to a specific process.
 Mapping symbolic layout to a specific process
technology uses 10–20 percent more area than hand-
crafted layout (though this can then be further
reduced to 5–10 percent with compaction).
 Most symbolic layout systems do not allow 45° layout
and this introduces a further area penalty (my
experience shows this is about 5–15 percent).
 As libraries get larger, and the capability to quickly
move libraries and ASIC designs between different
generations of process technologies becomes more
important, the advantages of symbolic layout may
outweigh the disadvantages.
Logic Synthesis
• Designers are increasingly using logic synthesis as a
replacement for schematic entry.
• As microelectronic systems and their ASICs become
more complex, the use of schematics becomes less
practical.
• For example, a complex ASIC that contains over
10,000 gates might require hundreds of pages of
schematics at the gate level.
• As another example, it is easier to write A = B + C
than to draw a schematic for a 32-bit adder at the
gate level.
• The term logic synthesis is used to cover a broad
range of software and software capabilities.
•Many logic synthesizers are based on logic minimization.
•Logic minimization is usually performed in one of two
ways, either using a set of rules or using algorithms.
Early logic-minimization software was designed using
algorithms for two-level logic minimization and developed
into multilevel logic-optimization software.
Two-level and multilevel logic minimization is well suited
to random logic that is to be implemented using a CBIC,
MGA, or PLD.
In these technologies, two-level logic can be implemented
very efficiently.
Logic minimization for FPGAs, including complex PLDs, is
more difficult than other types of ASICs, because of the
complex basic logic cells in FPGAs.
•There are two ways to use logic synthesis in the design of
FPGAs.
• The first and simplest method takes a hardware description,
optimizes the logic, and then produces a netlist.
•The netlist is then passed to software that maps the netlist
to an FPGA architecture.
•The disadvantage of this method is the inefficiency of
decoupling the logic optimization from the mapping step.
• The second, more complicated, but more efficient method,
takes the hardware description and directly optimizes the
logic for a specific FPGA architecture.
•Some logic synthesizers produce files in PALASM, ABEL, or
CUPL formats.
•Software provided by the FPGA vendor then take these files
and maps the logic to the FPGA architecture.
• The FPGA mapping software requires detailed
knowledge of the FPGA architecture.
• This makes it difficult for third-party
companies to create logic synthesis software
that can map directly to the FPGA.
• A problem with design-entry systems is the
difficulty of moving netlists between different
FPGA vendors.
•Once you have completed a design using an FPGA cell
library,
•for example, you are committed to using that type of
FPGA unless you repeat design entry using a different cell
library.
•ASIC designers do not like this approach since it exposes
them to the mercy of a single ASIC vendor.
•Logic synthesizers offer a degree of independence from
FPGA vendors by delaying the point in the design cycle at
which designers need to make a decision on which FPGA
to use. Of course, now designers become dependent on
the synthesis software company.
FPGA Synthesis
•For low-level logic synthesis, PALASM is a de facto standard as the
lowest-common-denominator interchange format.
•Most FPGA design systems are capable of converting their own
native formats into a PALASM file.
•The most common programmable logic design systems are ABEL
from Data I/O, CUPL from P-CAD, LOG/iC from IsData, PALASM2
from AMD, and PGA-Designer from Minc.
•At a higher level, CAD companies (Cadence, Compass, Mentor, and
Synopsys are examples) support most FPGA cell libraries.
•This allows you to map from a VHDL or Verilog description to an
EDIF netlist that is compatible with FPGA design software.
•Sometimes you have to buy the cell library from the software
company, sometimes from the FPGA vendor.
The Halfgate ASIC
•The hidden details of the design and construction of this “halfgate
FPGA” are quite complicated.
•Fortunately, most of the inner workings of the design software are
normally hidden from the designer.
•However, when software breaks, as it sometimes does, it is
important to know how things work in order to fix the problem.
•The formats, filenames, and flow will change, but the information
needed at each stage and the order in which it is conveyed will stay
much the same.
The halfgate ASIC design illustrates the differences between a
nondeterministic coarse-grained FPGA (Xilinx XC4000), a
nondeterministic fine-grained FPGA (Actel ACT 3), and a
deterministic complex PLD (Altera MAX 7000).
These differences, summarized as follows, were apparent even in
the halfgate design:
The Xilinx LCA architecture does not permit an accurate timing
analysis until after place and route.
This is because of the coarse-grained nondeterministic architecture.
The Actel ACT architecture is nondeterministic, but the fine-grained
structure allows fairly accurate preroute timing prediction.
The Altera MAX complex PLD requires logic to be fitted to the
product steering and programmable array logic.
The Altera MAX 7000 has an almost deterministic architecture,
which allows accurate preroute timing.
Low-Level Design Languages
•Schematics can be a very effective way to convey design
information because pictures are such a powerful medium.
•There are two major problems with schematic entry, however.
•The first problem is that making changes to a schematic can be
difficult.
•When you need to include an extra few gates in the middle of a
schematic sheet, you may have to redraw the whole sheet.
•The second problem is that for many years there were no standards
on how symbols should be drawn or how the schematic information
should be stored in a netlist.
•These problems led to the development of design-entry tools
based on text rather than graphics.
•As TTL gave way to PLDs, these text-based design tools became
increasingly popular as de facto standards began to emerge for the
format of the design files.
•PLDs are closely related to FPGAs.
•The major advantage of PLD tools is their low cost, their ease of use,
and the tremendous amount of knowledge and number of designs,
application notes, textbooks, and examples that have been built up
over years of their use.
•It is natural then that designers would want to use PLD
development systems and languages to design FPGAs and other
ASICs.
•For example, there is a tremendous amount of PLD design expertise
and working designs that can be reused.
•In the case of ASIC design it is important to use the right tool for the
job. This may mean that you need to convert from a low-level design
medium you have used for PLD design to one more appropriate for
ASIC design
Languages that are used are
• 1.ABEL : ABEL is a PLD programming language
from Data I/O.
• CUPL : CUPL is a PLD design language from
Logical Devices
• PALASM : PALASM is a PLD design language
from AMD/MMI.
PLA Tools
• We shall use the Berkeley PLA tools to illustrate
logic minimization using an example to minimize
the logic required to implement the following three
logic functions:
• F1 = A|B|!C; F2 = !B&C; F3 = A&B|C;
• These equations are in eqntott input format.
The eqntott (for “equation to truth table”) program
converts the input equations into a tabular format.
• Table 9.8 shows the truth table and eqntott output
for functions F1 , F2 , and F3 that use the six
minterms: A , B , !C , !B&C , A&B , C .
Output (5 minterms):
F1 = A|!C|(B&C);
F2 = !B&C;
F3 =
A&B|(!B&C)|(B&C);
• This eqntott output is not really a truth table
since each line corresponds to a minterm.
• The output forms the input to
the espresso logic-minimization program.
• below Table shows the format
for espresso input and output files.
 # comment # must be first character on a line.

[d] Decimal number

[s] Character string
.i [d] Number of input variables
.o [d] Number of output variables
.p [d] Number of product terms

.ilb [s1] [s2]... [sn] Names of the binary-valued variables must be after .i and .o .

.ob [s1] [s2]... [sn] Names of the output functions must be after .i and .o .

.type f Following table describes the ON set; DC set is empty.

.type fd Following table describes the ON set and DC set.

.type fr Following table describes the ON set and OFF set.

.type fdr Following table describes the ON set, OFF set, and DC set.

.e Optional, marks the end of the PLA description.

The format of the plane part of the input and output files for espresso.
Plane Character Explanation
I 1 The input literal appears in the product term.

The input literal appears complemented in the

I 0
product term.

I - The input literal does not appear in the product term.

O 1 or 4 This product term appears in the ON set.

O 0 This product term appears in the OFF set.

O 2 or - This product term appears in the don’t care set.

O 3 or ~ No meaning for the value of this function.

F1 = A|!C|(B&C); F2 = !B&C; F3 = A&B|(!B&C)|(B&C);
We see that espression reduced the original six minterms to
these five: A , A&B , !C , !B&C , B&C .
The Berkeley PLA tools were widely used in the 1980s.
They were important stepping stones to modern logic
synthesis tools.
There are so many testbenches, examples, and old designs
that used these tools that we occasionally need to convert
files in the Berkeley PLA format to formats used in new
tools.
 EDIF (Electronic Design Interchange Format)
• An ASIC designer spends an increasing amount of time forcing
different tools to communicate.
• One standard for exchanging information between EDA tools is
the electronic design interchange format (EDIF )
• The most important features added in EDIF 3 0 0 were to handle
buses, bus rippers, and buses across schematic pages.
• EDIF 4 0 0 includes new extensions for PCB and multichip module
(MCM) data.
• The Library of Parameterized Modules ( LPM ) standard is also
based on EDIF.
• The newer versions of EDIF have a richer feature set, but the ASIC
industry seems to have standardized on EDIF 2 0 0.
• Most EDA companies now support EDIF. The FPGA
companies Altera and Actel use EDIF as their netlist
format, and Xilinx has announced its intention to
switch from its own XNF format to EDIF.
• We only have room for a brief description of the EDIF
format here.
• A complete description of the EDIF standard is
contained in the Electronic Industries
Association ( EIA ) publication, Electronic Design
Interchange Format Version 2 0 0 ( ANSI/EIA Standard
548-1988) [ EDIF, 1988].

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 EDIF Syntax
• The structure of EDIF is similar to the Lisp programming
language or the Postscript printer language.
• This makes EDIF a very hard language to read and
almost impossible to write by hand.
• EDIF is intended as an exchange format between tools,
not as a design-entry language.
• Since EDIF is so flexible each company reads and writes
different “flavors” of EDIF.
• Inevitably EDIF from one company does not quite work
when we try and use it with a tool from another
company, though this situation is improving with the
gradual adoption of EDIF 3 0 0.
• We need to know just enough about EDIF to be able to
fix these problems.
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• Within an EDIF file are one or more libraries
of cell descriptions.
• Each library contains technology information
that is used in describing the characteristics
of the cells it contains.
• Each cell description contains one or more
user-named views of the cell.
• Each view is defined as a
particular viewType and contains
an interface description that identifies where
the cell may be connected to and, possibly,
a contents description that identifies the
components and related interconnections that
make up the cell.

The EDIF syntax consists of a series of statements in the following format:

(keywordName {form})

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• The semantics of EDIF are defined by the EDIF
keywords . Keywords are the only types of name that
can immediately follow a left parenthesis. Case is not
significant in keywords.
• An EDIF identifier represents the name of an object or
group of data. Identifiers are used for name definition,
name reference, keywords, and symbolic constants.
• Valid EDIF identifiers consist of alphanumeric or
underscore characters and must be preceded by an
ampersand ( &) if the first character is not alphabetic.
• The ampersand is not considered part of the name.
The length of an identifier is from 1 to 255 characters
and case is not significant.
• Thus &clock , Clock , and clock all represent the same
EDIF name
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• Numbers in EDIF are 32-bit signed integers.
• Real numbers use a special EDIF format.
• For example, the real number 1.4 is represented
as (e 14 -1)
• Numbers in EDIF are dimensionless and the units
are determined according to where the number
occurs in the file.
• Coordinates and line widths are units of distance
and must be related to meters.
• The scalekeyword is used with
the numberDefinition to relate EDIF numbers to
physical units.
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• Valid EDIF strings consist of sequences of ASCII
characters enclosed in double quotes.
• Any alphanumeric character is allowed as well as any of
the following characters: ! # $ & ' () * + , - . / : ; < = > ?
@ [ \ ] ^ _ ` { | } ~ . Special characters, such
as " and % are entered as escape
sequences: %number% , where number is the integer
value of the ASCII character.
• For example, "A quote is % 34 %" is a string with an
embedded double-quote character.
• Blank, tab, line feed, and carriage-return characters
(white space) are used as delimiters in EDIF.
• Blank and tab characters are also significant when they
appear in strings.

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• The rename keyword can be used to create a
new EDIF identifier as follows:
• (cell (rename TEST_1 "test$1") ...

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 An EDIF Schematic Icon

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LOGIC SYNTHESIS
• Logic synthesis provides a link between an HDL (Verilog or VHDL)
and a netlist.
• However, the parallel is not exact.
• C was developed for use with compilers, but HDLs were not
developed for use with logic-synthesis tools.
• Verilog was designed as a simulation language and VHDL was
designed as a documentation and description language.
• Both Verilog and VHDL were developed in the early 1980s, well
before the introduction of commercial logic-synthesis software.
• Because these HDLs are now being used for purposes for which
they were not intended, the state of the art in logic synthesis falls
far short of that for computer-language compilers.
• Logic synthesis forces designers to use a subset of both Verilog
and VHDL, This makes using logic synthesis more difficult .
• When talking to a logic-synthesis tool using an
HDL, it is necessary to think like hardware,
anticipating the netlist that logic synthesis will
produce.
• This situation should improve in the next five
years, as logic synthesizers mature.
• Designers use graphic or text design entry to
create an HDL behavioral model , which does not
contain any references to logic cells
• State diagrams, graphical data path descriptions,
truth tables, RAM/ROM templates, and gate-level
schematics may be used together with an HDL
description.
Once a behavioural HDL model is complete, two items are
required to proceed:
A logic synthesizer (software and documentation) and a
cell library (the logic cells—NAND gates and such) that is
called the target library .
The behavioural model is simulated to check that the
design meets the specifications and then the logic
synthesizer is used to generate a net list, a structural
model , which contains only references to logic cells.
There is no standard format for the net lists that logic
synthesis produces, but EDIF is widely used.
Verilog and Logic Synthesis
• A top-down design approach using Verilog begins with
a single module at the top of the hierarchy to model
the input and output response of the ASIC:
• module MyChip_ASIC(); ... (code to model ASIC I/O)
... endmodule ;
• This top-level Verilog module is used to simulate the
ASIC I/O connections and any bus I/O during the
earliest stages of design.
• Often the reason that designs fail is lack of attention to
the connection between the ASIC and the rest of the
system.
• As a designer, you proceed down through the hierarchy
as you add lower-level modules to the top-level Verilog
module
Initially the lower-level modules are just empty placeholders,
orstubs , containing a minimum of code.
For example, you might start by using inverters just to
connect inputs directly to the outputs.
You expand these stubs before moving down to the next level
of modules.
module MyChip_ASIC()
// behavioral "always", etc. ...
SecondLevelStub1 port mapping
SecondLevelStub2 port mapping
... endmodule
module SecondLevelStub1() ... assign Output1 = ~Input1; endmodule
module SecondLevelStub2() ... assign Output2 = ~Input2; endmodule
Eventually the Verilog modules will correspond to the various
component pieces of the ASIC.
Verilog Modeling
•Before we could start synthesis of the Viterbi decoder we
had to alter the model for the D flip-flop.
•This was because the original flip-flop model contained
syntax (multiple wait statements in an always statement) that
was acceptable to the simulation tool but not by the synthesis
tool.
•However, finding ourselves with non-synthesizable code
arises frequently in logic synthesis.
•The original OVI LRM included a synthesis policy , a set of
guidelines that outline which parts of the Verilog language a
synthesis tool should support and which parts are optional.
•There is no current standard on which parts of an HDL
(either Verilog or VHDL) a synthesis tool should support.
 D FLIP-FLOP

• module dff(D,Q,Clock,Reset); // N.B. reset is

active-low
• output Q; input D,Clock,Reset;
• parameter CARDINALITY = 1; reg [CARDINALITY-1:0] Q;
• wire [CARDINALITY-1:0] D;
• always @( posedge Clock) if (Reset!==0) #1 Q=D;
• always begin wait (Reset==0);
Q=0; wait (Reset==1); end
• endmodule
 D FLIP-FLOP - MODEFIED
• module dff(D, Q, Clk, Rst); // new flip-flop for
Viterbi decoder
• parameter width = 1, reset_value =
0; input [width - 1 : 0] D;
• output [width - 1 : 0] Q; reg [width - 1 : 0]
Q; input Clk, Rst;
• initial Q <= {width{1'bx}};
• always @ ( posedge Clk or negedge Rst )
• if ( Rst == 0 ) Q <= #1 reset_value; else Q <= #1 D;
• endmodule
•It is essential that the structural model created by a synthesis
tool is functionally identical , or functionally equivalent , to
your behavioral model.
•Hopefully, we know this is true if the synthesis tool is
working properly. In this case the logic is “correct by
construction.”
•If you use different HDL code for simulation and for
synthesis, you have a problem.
• The process offormal verification can prove that two logic
descriptions (perhaps structural and behavioral HDL
descriptions) are identical in their behavior.