Architecture of 8086

Introduction of 8086
• 8086 Microprocessor is an enhanced version of 8085Microprocessor
that was designed by Intel in 1976.
• It is a 16-bit Microprocessor having 20 address lines and16 data lines
that provides up to 1MB storage.
• The 20 address lines are time multiplexed lines. The 16 low order
address lines are time multiplexed with the data lines and the 4 high
order address lines are time multiplexed with status lines.
• It provides 16 -bit registers and word size is of 16 bit.
• It consists of powerful instruction set, which provides operations like
multiplication and division easily.
 Contd.
• 8086 is designed to operate in two modes, Minimum and Maximum.
Minimum mode is designed for single processor environment i.e. only one
8086 CPU is to be used in microcomputer system, while maximum mode is
designed for multiprocessor environment.
• It has an instruction queue, which is capable of storing six instruction bytes
from the memory resulting in faster processing.
• It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.
• It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which
improves performance.
• Fetch stage can prefetch up to 6 bytes of instructions and stores them in
the queue and execute stage executes these instructions.
8086 Internal Architecture
 Bus Interface Unit (BIU)
• The BIU performs all bus operations such
as instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands.
• It computes and sends out addresses,
fetches instruction codes, store fetched
instruction codes in register set, reading
data from the ports and the memory as
well as writing data to the ports and the
memory.
• EU has no direct connection with System
Buses so this is possible with the BIU. EU
and BIU are connected with the Internal
Bus.
 Contd.
• Both units operate asynchronously to give the 8086 an overlapping
instruction fetch and execution mechanism which is called as
Pipelining. This results in efficient use of the system bus and system
performance.
• BIU contains Instruction queue, Segment registers, Instruction
pointer, Address adder, a full 16 bit bidirectional data bus and 20 bit
address bus.
• EU contains Control circuitry, Instruction decoder, ALU, Pointer and
Index register, Flag register.
 Parts of 8086
• It has the following functional parts −
1. Instruction queue
• BIU contains the instruction queue. It gets up to 6 bytes of next instructions and
stores them in the instruction queue.
• With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory
cycle.
• The EU accesses the queue from the output end. It reads one instruction byte
after the other from the output of the queue
• When EU executes instructions and is ready for its next instruction, then it simply
reads the instruction from this instruction queue resulting in increased execution
speed.
• Fetching the next instruction while the current instruction executes is
called pipelining.
 2.Segment registers
• The memory in an 8086/88 based system is organized as segmented
memory.
• The CPU 8086 is able to address 1Mbyte of memory but this
complete physically available memory is divided into a number of
logical segments.
• The size of each segment is 64 KB and a segment may be located any
where in the memory.
• Each of these segments can be used for a specific function.
• The 4 segments are Code, Data, Extra and Stack segments each of
64Kb block of memory.
 Contd.
• Code segment is used for storing the instructions i.e. where the executable
program is stored. The processor uses CS segment for all accesses to instructions
referenced by instruction pointer (IP) register.
• The stack segment is used as a stack and it is used to store the return addresses.
By default, the processor assumes that all data referenced by the stack pointer
(SP) and base pointer (BP) registers is located in the stack segment.
• The data and extra segments are used for storing data byte. By default, the
processor assumes that all data referenced by general registers (AX, BX, CX, DX)
and index register (SI, DI) is located in the data segment.
• To specify where in the 1MB of processor memory these 4 segments are located,
the processor uses four segment registers:
1. Code Segment Register
2. Stack Segment Register
3. Data Segment Register
4. Extra Segment Register
• The 16 bit contents of the segment registers in the BIU actually point to the
starting location of a particular segment.
 Contd.
• Each of the Segment registers store the upper 16 bit address of the
starting address of the corresponding segments.
 3. Instruction Pointer
• The instruction Pointer (IP) in 8086 acts as program counter. It points to the
address of the next instruction to be executed. Its contents are automatically
incremented when the execution of a program proceeds.
• The contents of the IP and code segment register are used to compute the
memory address of the instruction code to be fetched.
• The IP register hold the 16 bit offset address or the offset, of the next code byte
within the Code segment.
• An offset is the distance (in terms of address) from the beginning of a segment to
a particular instruction or variable.
• The physical address of the next instruction is formed by combining the CS and IP.
• To form a 20bit address of the next instruction, the 16 bit address of the IP is
added (by the address summing block) to the address contained in the CS , which
has been shifted four bits to the left.
 4. Address Generation Circuit (Adder)
• The BIU has a Physical Address Generation Circuit.
• It generates the 20 bit physical address using Segment and Offset
addresses using the formula: Physical Address = Segment Address x
10H + Offset Address
EXECUTION UNIT
 EXECUTION UNIT
• The execution unit includes the
1. ALU,
2. Four 16-bit general purpose registers
3. Four 16- bit pointers and index registers
4. 16-bit flag register and
5. Control unit.
• EU contains control circuitry which directs internal operations.
• A decoder in the EU translates instructions fetched from memory into
a series of actions which the EU carries out.
• The EU has a 16-bit arithmetic logic unit which can add, subtract,
AND, OR, increment, decrement, complement, Binary numbers.
 EXECUTION UNIT-General Purpose Registers
• The EU contains Four 16-bit general purpose registers AX, BX, CX, DX.
• These registers AX, BX, CX, DX can be further divided into two 8-bit
registers AH & AL, BH & BL, CH & CL and DH & DL.
• These registers can be used individually to store 8-bit data and can be
used in pairs to store 16-bit data.
 Contd.
• AX register − It is also known as accumulator register. It is used to
store operands for arithmetic operations.
• BX register − It is used as a base register. It is used to store the
starting base address of the memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction
to store the loop counter.
• DX register − This register is used as data register, used to hold I/O
port address for I/O instruction.
 EU--Pointer and Index Registers
• There are four pointer and index registers, which are
1. Stack Pointer(SP)
2. Base Pointer(BP)
3. Source Index(SI)
4. Destination Index(DI)
• They are used to keep offset addresses within the stack , data and extra
segment so used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a physical address is
the Stack Segment. SP is used with SS to access the stack segment , while
BP is primarily used to access data on the stack.
• The index registers (SI & Di) and the BX generally default to the Data
segment register(DS) and Extra Segment register.
 EU--Pointer and Index Registers
• Stack Pointer (SP) is a 16-bit register pointing to program stack. Stack is a set of
memory locations operating in LIFO manner. Stack is present in the memory in
Stack Segment. It is used during instructions like PUSH, POP, CALL, RET etc.
• Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP can
hold offset address of any location in the stack segment. It is used to access
random locations of the stack.
• Source Index (SI) is a 16-bit register. It is normally used to hold the offset address
for Data Segment but can also be used for other segments using Segment
Overriding. It holds offset address of source data in Data Segment during string
operations.
• Destination Index (DI) is a 16-bit register. It is normally used to hold the offset
address for Extra Segment but can also be used for other segments using
Segment Overriding. It holds offset address of destination in Extra Segment
during string operations.
 EU-- Pointer And Index Registers
• SI: Source Index register, the SI register points to memory locations in
the data segment which is addressed by the DS register. By
incrementing the contents of SI consecutive memory locations can be
accessed.
• DI: Destination Index register, the DI register points to memory
locations in the data segment which is addressed by the ES register.
Thus, DI is associated with the ES in string operations.
• The SI and the DI registers may also be used to access data stored in
arrays.
 Flag register
• The 8086 has nine 1 bit flags. Out of 9 six are status and three are control
flags.
• The control bits in the flag register can be set or reset by the programmer.
• O-Overflow flag This flag is set if an arithmetic overflow occurs, i.e. if the
result of a signed operation is large enough to be accommodated in a
destination register.
• D-Direction Flag This is used by string manipulation instructions. If this flag bit is
‘0’ , the string is processed beginning from the lowest address to the higher
address, i.e. auto incrementing mode otherwise the string is processed from the
highest address towards the lowest address, i.e. auto decrementing mode
• I-Interrupt flag If this flag is set the maskable interrupts are recognized by
the CPU, otherwise they are ignored, i.e. to enable maskable interrupts.
 Flag register
• T-Trap flag If this flag is set the processor enters the single step execution mode. In other
words, a trap interrupt is generated after execution of each instruction. It allows user to
execute one instruction of a program at a time for debugging. The processor executes the
current instruction and the control is transferred to the Trap interrupt service routine.
• S -Sign flag This flag is set when the result of any computation is negative. For signed
computations, the sign flag equals the MSB of the result.
• Z-Zero This flag is set when the result of the computation is or comparison performed by the
previous instruction is zero. 1 for zero result, 0 fir nonzero result
• A-Auxiliary Carry This is set if there is a carry from the lowest nibble, i.e. bit three during
the addition or borrow for the lowest nibble i.e. bit three, during subtraction.
• P-Parity flag This flag is set to 1 if the lower byte of the result contains even number of 1s
otherwise reset.
• C-Carry flag This flag is set when there is a carry out of MSB in case of addition or a
borrow in case of subtraction.