Elmore Delay, Logical Effort

Modern Interconnect

© Rabaey, ch4Wire.ppt, slide 22

Example: Intel 0.25 micron Process

5 metal layers
Ti/Al - Cu/Ti/TiN
Polysilicon dielectric

© Rabaey, ch4Wire.ppt, slide 23

 Modern Interconnect
• 90nm process

© Chris Kim (image from Intel?)

The Lumped RC-Model, The Elmore Delay

(result *0.69)

© Rabaey, ch4Wire.ppt, slide 27

 Example: The Elmore Delay

Shared Paths:
R44 = R1+R3+R4
Rii = R1+R3+Ri
Ri4 = R1+R3
Ri2 = R1

Ti = C1R1 + C2R1 + C3(R1+R3) + C4(R1+R3) + Ci(R1+R3+Ri)

The Elmore Delay RC Chain

© Rabaey, ch4Wire.ppt
 The Distributed RC-line

Diffusion
Equation

© Rabaey, ch4Wire.ppt
Deriving the Diffusion Eq
Step-response of RC wire as
a function of time and space
2.5

x= L/10
2

x = L/4
voltage (V)

1.5

x = L/2
1
x= L
0.5

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
time (nsec)

© Rabaey, ch4Wire.ppt
RC-Models

© Rabaey, ch4Wire.ppt
 Driving an RC-line
Rs (r w,cw,L)
Vout

V
in

© Rabaey, ch4Wire.ppt
Designing Fast CMOS Gates

Slides from chapter6.ppt of

Rabaey’s page
 Fan-In Considerations

A B C D

A CL Distributed RC model
B C3 (Elmore delay)
C C2 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
D C1
Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 tp as a Function of Fan-In
1250
quadratic
1000
Gates with a
750
fan-in
tp (psec)

tpH tp greater than

500
L
4 should be
250 tpL avoided.
H linear
0
2 4 6 8 10 12 14 16
fan-in

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 tp as a Function of Fan-In and Fan-Out

 Fan-in: quadratic due to increasing

resistance and capacitance
 Fan-out: each additional fan-out gate
adds two gate capacitances to CL

tp = a1FI + a2FI2 + a3FO

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 1
 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 2
 Transistor ordering
critical path critical path

charged 01
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL

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EE141 Integrated Circuits2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 3
 Alternative logic structures
F = ABCDEFGH

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Fast Complex Gates:
Design Technique 4
 Isolating fan-in from fan-out using buffer
insertion

CL CL

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Logical Effort

Slides from chapter6.ppt of

Rabaey’s page
 Transistor Sizing
Cg=
Cint= Cg= Cint=
Cint= Cg=

D=1+f D=2+4/3 f D=2+5/3 f

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
Normalized Space
 Parasitic Term P

NOTE: p is a gate parameter  function(W)

Logical Effort Term g

NOTE: g is a gate parameter  function(W)

 Transistor Sizing a Complex
CMOS Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Logical Effort

From Sutherland, Sproull

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Logical Effort of Gates

2
=
p
3;
4/
5 1

=
p=

g
Normalized Delay

D:
4 AN 1;
g =
:
tN

e r
ert
pu

3 v
in

In Effort
2-

Delay
2

1
Intrinsic
Delay

1 2 3 4 5
Fanout f
© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 tp as a Function of Fan-Out

All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)

Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Buffer Example
In Out

1 2 N CL

N
Delay    pi  g i  f i  (in units of tinv)
i 1

For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Delay in a Logic Gate
Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay:
h=gf

logical effective fanout =

effort Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Add Branching Effort

Branching effort:

Con path  Coff  path

b
Con path

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Multistage Networks
N
Delay    pi  g i  f i 
i 1

Stage effort: hi = gifi

Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB

Path delay D = Sdi = Spi + Shi

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Optimum Effort per Stage

When each stage bears the same effort:

hN  H
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN

Effective fanout of each stage: f i  h g i

Minimum path delay

Dˆ   gi f i  pi   NH 1/ N  P

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Optimal Number of Stages
For a given load,
and given input capacitance of the first gate
Find optimal number of stages and optimal sizing

D  NH 1/ N  Npinv
D
N
 
  H 1/ N ln H 1/ N  H 1/ N  pinv  0

1/ Nˆ
Substitute ‘best stage effort’ hH

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EE141 Integrated Circuits2nd
Combinational Circuits
 Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F = 5
G=
H=
h=
a=
b=
c=
© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c

Effective fanout, F = 5
G = 25/9
H = 125/9 = 13.9
h = 1.93
a = 1.93
b = ha/g2 = 2.23
c = hb/g3 = 5g4/f = 2.59
© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Example – 8-input AND

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Method of Logical Effort

 Compute the path effort: F = GBH

 Find the best number of stages N ~ log4F
 Compute the stage effort f = F1/N
 Sketch the path with this number of stages
 Work either from either end, find sizes:
Cin = Cout*g/f

Reference: Sutherland, Sproull, Harris, “Logical Effort, Morgan-Kaufmann 1999.

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits
 Summary

Sutherland,
Sproull
Harris

© Digital
EE141 Integrated Circuits2nd
Combinational Circuits