Memory Organization 1 Lecture 42

Overview

 Memory Hierarchy

 Main Memory

 Auxiliary Memory

 Associative Memory

 Cache Memory

 Virtual Memory

 Memory Mgt Hardware

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Memory Organization 2 Lecture 42

Cache Memory
Locality of Reference
- The references to memory at any given time interval tend to be confined
within a localized areas
- This area contains a set of information and the membership changes
gradually as time goes by
- Temporal Locality
The information which will be used in near future is likely to be in use
already( e.g. Reuse of information in loops)
- Spatial Locality
If a word is accessed, adjacent(near) words are likely accessed soon
(e.g. Related data items (arrays) are usually stored together;
instructions are executed sequentially)
Cache
- The property of Locality of Reference makes the cache memory systems work
- Cache is a fast small capacity memory that should hold those information
which are most likely to be accessed

Main memory CPU

Cache memory

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Memory Organization 3 Lecture 42

Performance of Cache
Memory Access
All the memory accesses are directed first to Cache
If the word is in Cache; Access cache to provide it to CPU
If the word is not in Cache; Bring a block (or a line) including
that word to replace a block now in Cache

- How can we know if the word that is required is there ?

- If a new block is to replace one of the old blocks, which one should we choose ?

Performance of Cache Memory System

Hit Ratio - % of memory accesses satisfied by Cache memory system

Te: Effective memory access time in Cache memory system
Tc: Cache access time
Tm: Main memory access time

Te = Tc + (1 - h) Tm

Example: Tc = 0.4 s, Tm = 1.2s, h = 0.85%

Te = 0.4 + (1 - 0.85) * 1.2 = 0.58s
CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT
Memory Organization 4 Lecture 42

Memory and Cache Mapping – (Associative Mapping)

Mapping Function
Specification of correspondence between main memory blocks and cache blocks

Associative mapping
Direct mapping
Associative Mapping Set-associative mapping
- Any block location in Cache can store any block in memory
-> Most flexible
- Mapping Table is implemented in an associative memory
-> Fast, very Expensive
- Mapping Table
Stores both address and the content of the memory word
address (15 bits)

Argument register

Address Data
01000 3450
CAM 02777 6710
22235 1234

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Memory Organization 5 Lecture 42

Cache Mapping – direct mapping

- Each memory block has only one place to load in Cache
- Mapping Table is made of RAM instead of CAM
- n-bit memory address consists of 2 parts; k bits of Index field and n-k bits of Tag field
- n-bit addresses are used to access main memory and k-bit Index is used to access the Cache

Addressing Relationships Tag(6) Index(9)

00 000 32K x 12 000

512 x 12
Main memory Cache memory
Address = 15 bits Address = 9 bits
Data = 12 bits Data = 12 bits
77 777 777
Direct Mapping Cache Organization
Memory
address Memory data
Cache memory
00000 1220
Index
address Tag Data
00777 2340 000 00 1220
01000 3450

01777 4560
02000 5670

777 02 6710
02777 6710

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Memory Organization 6 Lecture 42

Cache Mapping – direct mapping

Operation

- CPU generates a memory request with (TAG;INDEX)

- Access Cache using INDEX ; (tag; data)
Compare TAG and tag
- If matches -> Hit
Provide Cache[INDEX](data) to CPU
- If not match -> Miss
M[tag;INDEX] <- Cache[INDEX](data)
Cache[INDEX] <- (TAG;M[TAG; INDEX])
CPU <- Cache[INDEX](data)

Direct Mapping with block size of 8 words

000 01 3450 Tag Block Word

Block 0
007 01 6578
010 INDEX
Block 1
017

Block 63 770 02
777 02 6710

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT

Memory Organization 7 Lecture 42

Cache Mapping – Set Associative Mapping

- Each memory block has a set of locations in the Cache to load

Set Associative Mapping Cache with set size of two

Index Tag Data Tag Data
000 01 3450 02 5670

777 02 6710 00 2340

Operation
- CPU generates a memory address(TAG; INDEX)
- Access Cache with INDEX, (Cache word = (tag 0, data 0); (tag 1, data 1))
- Compare TAG and tag 0 and then tag 1
- If tag i = TAG -> Hit, CPU <- data i
- If tag i  TAG -> Miss,
Replace either (tag 0, data 0) or (tag 1, data 1),
Assume (tag 0, data 0) is selected for replacement,
(Why (tag 0, data 0) instead of (tag 1, data 1) ?)
M[tag 0, INDEX] <- Cache[INDEX](data 0)
Cache[INDEX](tag 0, data 0) <- (TAG, M[TAG,INDEX]),
CPU <- Cache[INDEX](data 0)
CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT
Memory Organization 8 Lecture 42

Cache Write
Write Through
When writing into memory
If Hit, both Cache and memory is written in parallel
If Miss, Memory is written
For a read miss, missing block may be overloaded onto a cache block
Memory is always updated
-> Important when CPU and DMA I/O are both executing
Slow, due to the memory access time
Write-Back (Copy-Back)
When writing into memory
If Hit, only Cache is written
If Miss, missing block is brought to Cache and write into Cache
For a read miss, candidate block must be written back to the memory
Memory is not up-to-date, i.e., the same item in
Cache and memory may have different value

CSE 211, Computer Organization and Architecture Harjeet Kaur, CSE/IT