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Instruction Pipelining

Instruction pipelining is a technique where the instruction execution process is divided into multiple sequential stages. This allows subsequent instructions to begin execution before previous instructions have finished. A basic 5 stage pipeline includes fetch, decode, execute, memory, and writeback stages. Pipelining improves performance by allowing new instructions to begin processing every clock cycle rather than waiting for previous instructions to fully complete. However, hazards like structural hazards, data hazards, and control hazards can cause the pipeline to stall if instructions depend on one another. The MIPS architecture uses a 5 stage pipeline in its datapath to improve its performance through instruction pipelining.

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296 views

Instruction Pipelining

Instruction pipelining is a technique where the instruction execution process is divided into multiple sequential stages. This allows subsequent instructions to begin execution before previous instructions have finished. A basic 5 stage pipeline includes fetch, decode, execute, memory, and writeback stages. Pipelining improves performance by allowing new instructions to begin processing every clock cycle rather than waiting for previous instructions to fully complete. However, hazards like structural hazards, data hazards, and control hazards can cause the pipeline to stall if instructions depend on one another. The MIPS architecture uses a 5 stage pipeline in its datapath to improve its performance through instruction pipelining.

Uploaded by

Mahesh
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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INSTRUCTION PIPELINING

Presented by:- Roll no. GR No. Name


39 182202 Mahesh Khond
42 1710726 Pranav Kulkarni
43 1711074 Ranjeetsinh Lomte
72 182002 Vanchhita Wakode
Presentation Highlights

• Instruction pipelining
• MIPS pipelined data path
• Basic 5 stage pipeline
• Multicycle pipeline
• Performance improvement
• Hazards
Pipelining

• Pipelining is the process of accumulating and executing computer instructions


and tasks from the processor via a logical pipeline.
• It allows storing, prioritizing, managing and executing tasks and instructions in
an orderly process.
• Pipelining is also known as pipeline processing.
Understanding pipeline

• 4 loads of laundry that need to be washed, dried, and folded.


- 30 minutes to wash, 40 minutes to dry, and 20 minutes to fold.
- we have 1 washer, 1 dryer and 1 folding station.

• what’s the most efficient way to get 4 loads of laundry done?


Instruction Execution Cycle

• The time period during which one instruction is fetched from memory and
execute when computer given an instruction in machine language
• Each instruction is further divided into sequence of phases
• After the execution of instruction the program counter is incremented to point
the next instruction to be executed
Instruction Pipelining

• First stage fetches the instruction and buffers it.


• When the second stage is free the first stage passes it the buffered instruction.
• While the second stage is executing the instruction the first stage takes
advantages of any unused memory cycles to fetch and buffer the next
instruction.
• This is called instruction pre-fetch or fetch overlap.
Inefficiency in two stage instruction pipelining

• There are two reasons


• The execution time will be longer than fetch time .Thus fetch stage may have to
wait for some time before it can empty the buffer.
• When conditional branch occurs , then the address of next instruction to be
fetched become unknown .Then the execution stage have to wait while the next
instruction is fetched.
MIPS Definition

• MIPS stands for "Million Instructions Per Second."


• It is a method of measuring the raw speed of a computer's processor.
• The MIPS measurement has been used by computer manufacturers like IBM to
measure the "cost of computing."
MIPS pipelined datapath
Six stage of instruction pipelining

• Fetch instruction(FI): Instructions are fetched from the memory into a temporary buffer before
it gets executed.
• Decode instruction(DI): The instruction is decoded by the CPU so that the necessary op codes
and operands can be determined.
• Calculate operand(CO): Based on the addressing scheme used, either operands are directly
provided in the instruction or the effective address has to be calculated.
• Fetch Operand(FO): Once the address is calculated, the operands need to be fetched from the
address that was calculated. This is done in this phase.
• Execute Instruction(EI): The instruction can now be executed.
• Write operand(WO): Once the instruction is executed, the result from the execution needs to
be stored or written back in the memory.
Timing diagram for instruction pipeline
Instruction pipelining
Diagram
Advantages

• Pipelining makes efficient use of resources.


• Quicker time of execution of large number of instructions.
• The parallelism is invisible to the programmer
Hazards

• Structural hazards: attempt to use the same resource by two different


instructions at the same time .
• Data hazards: attempt to use data before it is ready - An instruction’s source
operand(s) are produced by a prior instruction still in the pipeline.
• Control hazards: attempt to make a decision about program control flow before
the condition has been evaluated and the new PC target address calculated -
branch instructions.
Reference

• https://www.slideshare.net/SaidurRahmanKohinoor/instruction-pipeline-
computer-architecture?from_action=save
• https://www.google.com/url?sa=i&source=images&cd=&cad=rja&uact=8&ved=
2ahUKEwip7eOOzP3lAhVkILcAHU-
pAMwQjhx6BAgBEAI&url=https%3A%2F%2Fptop.only.wip.la%3A443%2Fhttps%2Fwww.slideshare.net%2Futsav_shah
%2Finstruction-execution
• The 8051 Microcontroller and Embedded Systems By M. Mazidi, j. Mazidi
THANK YOU
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