Scribd
Upload
115 views16 pages

FPGA Slides

FPGAs allow users to configure digital circuits by programming configurable logic blocks and interconnects. An FPGA contains an array of CLBs that can be programmed to emulate different logic functions using lookup tables and multiplexers. The CLBs are connected through a programmable interconnect that is configured by loading a bitstream file. FPGA design tools hide the complexity of placement, routing, and bitstream generation from the user.

Uploaded by

Aashrey Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
115 views16 pages

FPGA Slides

FPGAs allow users to configure digital circuits by programming configurable logic blocks and interconnects. An FPGA contains an array of CLBs that can be programmed to emulate different logic functions using lookup tables and multiplexers. The CLBs are connected through a programmable interconnect that is configured by loading a bitstream file. FPGA design tools hide the complexity of placement, routing, and bitstream generation from the user.

Uploaded by

Aashrey Jain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 16

Introduction to FPGAs

Thanks to him for this slides


Dr. Konstantinos Tatas
[email protected]
http://staff.fit.ac.cy/com.tk
Objectives

• Design and implementation of a simple CPU


• Hardware: Xilinx Spartan-3E Starter Kit
• Software: Xilinx ISE
Xilinx Spartan-3E Starter Kit

FPGA

buttons LEDs
switches
FPGA Principles
• A Field-Programmable Gate Array (FPGA)
is an integrated circuit that can be
configured by the user to emulate any
digital circuit as long as there are enough
resources

• An FPGA can be seen as an array of


Configurable Logic Blocks (CLBs)
connected through programmable
interconnect (Switch Boxes)
FPGA structure

CLB SB CLB

SB SB SB

Configurable Logic Blocks


CLB SB CLB

Interconnection Network

I/O Signals (Pins)


Simplified CLB Structure
Look-Up MUX
SET
Table D Q
(LUT)

CLR Q
CLB SB CLB

SB SB SB

Configurable Logic Blocks


CLB SB CLB

Interconnection Network

I/O Signals (Pins)


A
Example: 4-input AND gate
B
O
C
D

A B C D O
0 0 0 0 0
0 0 0 1 0 0
0
0 0 1 0 0 0
A 0
MUX O
0 0 1 1 0 0
0 SET
0 1 0 0 0 B 0 D Q
0
0 1 0 1 0 0
C 0
0
0 1 1 0 0 0 CLR Q
0 1 1 1 0 D 0
0 0
0
1 0 0 0 0 1

1 0 0 1 0
1 0 1 0 0 Configuration bits
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 1
Example 2: Find the configuration
bits for the following circuit
A0

2-to-1 SET
MUX
D Q

A1

CLR Q

S A0 MUX
Clock SET
A1 D Q
A0 A1 S
S
0 0 0
CLR Q
0 0 1
0 1 0
0 1 1
1 0 0
Configuration bits
1 0 1
1 1 0
1 1 1
Interconnection Network
Configuration
bits 0 1
0

CLB SB CLB 0
0 0

SB SB SB

Configurable Logic Blocks


CLB SB CLB

Interconnection Network

I/O Signals (Pins)


Example 3
• Determine the configuration bits for the following circuit
implementation in a 2x2 FPGA, with I/O constraints as shown in the
following figure. Assume 2-input LUTs in each CLB.
Input1

Input2
CLB0 SB0 CLB1
Input1 D
SET
Q
Input2 Output
Q
Input3 CLR

SB1 SB2 SB3

Input3
CLB2 SB4 CLB3 Output
CLBs required
CLB 1 CLB 2
Input1 D
SET
Q
Input2 Output
CLR Q

Input3

0
0
MUX O MUX Output
SET
0 D Q D
SET
Q
Input1 O 1
Input2 0 Input3 1
CLR Q CLR Q
1 0
1 0

Configuration bits Configuration bits


Placement: Select CLBs
Input1

Input2
CLB0 SB0 CLB1

SB1 SB2 SB3

Input3
CLB2 SB4 CLB3 Output
Routing: Select path
Input1
SB1

Configuration bits

Input2
CLB0 SB0 CLB1
0 0
0

1
0 0
SB1 SB2 SB3

SB4

Configuration bits
Input3
CLB2 SB4 CLB3 Output

0 0
1

0
0 0
Configuration Bitstream
• The configuration bitstream must include ALL CLBs and
SBs, even unused ones
• CLB0: 00011
• CLB1: 01100
• CLB2: XXXXX
• CLB3: ?????
• SB0: 000000
• SB1: 000010
• SB2: 000000
• SB3: 000000
• SB4: 000001
Realistic FPGA CLB: Xilinx
FPGA EDA Tools
• Must provide a design environment based
on digital design concepts and
components (gates, flip-flops, MUXs, etc.)

• Must hide the complexities of placement,


routing and bitstream generation from the
user. Manual placement, routing and
bitstream generation is infeasible for
practical FPGA array sizes and circuit
complexities.

You might also like