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 Maryam Khalid
 Amina Ahsan
 M Afaq Azhar
 Mohabbat Rasool

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History Of RISC
 The Search for RISC
 RISC Characteristics
 Bus Architecture
 Pipeline Architecture
Define Pentium
Pentium Processor Architecture
Pentium Registers
Segmented Addressing
 1975 801 project initiated at IBM’s Watson Research
Center.
 1979 32-bit RISC microprocessor (801) developed led
by Joel Birnbaum.
 1984 MIPS (Microprocessor without Interlocked
Pipeline Stages) developed at Stanford, as well as
projects done at Berkeley.
 1988 RISC processors had taken over high-end of the
workstation market.

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RISC Stands for Reduced Instruction Set Computer.
 It is a microprocessor that is designed to perform a
smaller number of types of computer instruction so that
it can operate at a higher speed.

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 Relatively few instructions
 128 or less
 Relatively few addressing modes
 Memory access is limited to LOAD and STORE
instructions
 All operations done within the registers of the CPU
 This architectural feature simplifies the instruction set
and encourages the optimization of register
manipulation

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 Fixed Length, easily decoded instruction format.
 Single cycle instruction execution.
 Done by overlapping the fetch, decode and execute
phases of two or three instructions known as
Pipelining.
 Large number of registers in the processor unit.

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 Bus Interconnection of Processor units to memory and
IO subsystem

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Memory Bus:
 Memory bus (also called system bus since it
interconnects the subsystems)
 Interconnects the processor with the memory systems
and also connects the I/O bus.
 Three sets of signals –address bus, data bus and control
bus

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 System Bus :
 A system’s bus characteristics --- according to the
needs of the processor, speed, and word length for
instructions and data.
 Processor internal bus(es) characteristics differ from
the system external bus(es).

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 Buses to interconnect the processor Functional units to
memory and IO subsystem

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 Address Bus:
 Processor issues the address of the instruction byte or
word to the memory system through the address bus

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Data Bus:
 When the Processor issues the address of the
instruction, it gets back the instruction through the data
bus When it issues the address of the data, it loads the
data through the data bus.

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Control Bus:
 Issues signals to control the timing of various actions
during interconnection.
 Bus signals synchronize the subsystems.

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 A technique used in advanced microprocessors where
the microprocessor begins executing a second
instruction before the first has been completed.
 A Pipeline is a series of stages, where some work is
done at each stage. The work is not finished until it has
passed through all stages.

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 Structure:

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 A family of 32 and 64-bit x86-based CPU
chips from Intel.
 The term may refer to the chip or to a PC that
uses it.
 The Pentium is a widely-used personal
computer microprocessor from the Intel
Corporation.

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 First offered in 1993, the Pentium quickly
replaced Intel's 486 microprocessor as the
microchip-of-choice in manufacturing a personal
computer.
 The original Pentium model includes two
processors on one chip that contains 3.1
million transistors.
 The Pentium Pro, released in 1995, was designed
for PC servers and workstation that needed to
serve multiple users or needed the speed
required for graphics-intensive applications.

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 In addition to the microprocessor, the
Pentium Pro includes another microchip
containing cache memory that, being closer
to the processor than the computer's main
memory (RAM), speeds up computer
operation. The Pentium Pro contains 5.5
million transistors.

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 Instructions are Fetched from the code cache or from
the external bus.
 The decode unit Decodes the prefetched instructions so
the Pentium processor can execute the instruction
 Branch prediction is implemented with 2 Prefetch
Buffers and a Branch Target Buffer so the needed code
is almost always prefetched before it is needed for
execution.

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 Instructions are executed in 1 of 2 pipelines (“u” & “v”
pipes) which share access to a single set of registers. –
No additional instructions can begin execution until
both execution units complete their operations.
 Pentium processors have two instruction pipelines.
 The u-pipe can Execute all integer and floating point
instructions.
 The v-pipe can Execute simple integer instructions and
the FXCH floating-point instructions.

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 Pairing instructions in these two pipes enables the
Pentium to operate on 2 instructions at the same time
(Superscaler execution).
 The Control ROM unit has direct control over both
pipelines.
 The Control ROM contains microcode which controls
the sequence of operations that must be performed.

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 16-BIT
 AX
 DX
 CX
 BX

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 32-BIT
 EAX
 EDX
 ECX
 EBX
 EBP
 ESI
 EDI
 ESP

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