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 System Specification

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Verilog Module
Signifies declaration of a module
Name assigned to the module
Port declaration of the
Module name (ports); module

port declarations; Port direction declaration

other declarations;

statements; The semicolon ‘;’ signifies

statements; termination of a module
statement

Individual statement s
within the module
endmodule
Signifies termination of a module
Port Declarations
SYNTAX
 INPUT input a, b;

 OUTPUT

 INOUT

 WIRE

 REG
Identifiers
 Identifiers are names given to objects so that they can
be referenced in the design.
 Identifiers can start with an alpha character (a-z, A-Z)
or an underscore (_).
 Identifiers contain alphanumeric, dollar signs ($), and
underscores.
 Identifiers can be up to 1023 characters long.
 Names of instances, modules, nets, ports, and
variables are identifiers.
 Verilog is case sensitive, sel and SEL are different
identifiers.
Keywords
 Keywords are special identifiers reserved to define the
language constructs.

 Keywords are lowercase letters.

 Keywords cannot be used as Identifiers that is module

is a keyword but MODULE can be an Identifier, though
it is better not to use them so as to avoid confusion.
Comments
 Comments can be inserted in the code for readability
and documentation.
 Begin a single-line comment with // and end it with the
new-line character.
 Begin a multi-line comment with /* and end it with */.

Examples:
// Single line comment
/* Another single line comment */
/* Begins multi-line (block) comment
All text within is ignored
Line below ends multi-line comment */
Number Specification
 They are of two types
Sized Numbers
Un-sized Numbers

Sized Numbers:
Syntax:<size>'<baseformat><number>

4’b1111 => this is a 4-bit binary number

12’habc => this is a 12-bit hexadecimal number
16’d225 => this is a 16-bit decimal number
12’h13x => this is a 12-bit hexadecimal number
Numbers
<Size>’<base><number>

Number of Bits Consecutive 8’hax = 1010xxx

characters 0-f,x,z
12’o3zx7=011zzzxxx111
Binary-b or B
Octal – o or O
Decimal- d or D
Hexadecimal –h or H
 Values
 Values:0 1 X Z
 0- Represents a logic Zero,or a false condition
 1-Represnts a logic ONE, or a True Statement
 X- Represents an Unknown logic value.
 Z-Represents a High Impedance state.
 Strengths :
 Strongest signal Prevails
 Useful for gate level modeling and not for RTL
Regs-(reg Data type)
 Reg data types do not yield hardware registers
 Values retained until updated
 Assignments – Registers and nets can be mixed

Wire a;
Reg b;

a=b; b=a;

Wire Y;
Reg A,B; Type
declaration
Syntax to declare a net
Syntax:
net_type [range] list_of_variables;

 Declare the net type

You can optionally declare a [MSB:LSB] range.
You can declare multiple nets of the same type and
range.

Examples:
wand w; // A scalar net of type "wand"
tri [15:0] bus; // A 16-bit three-state bus
wire [0:31] w1, w2; // Two 32-bit wires with msb = bit 0
wire #5 addr_sel; // A scalar wire with a delay
Different Types of Operators
Type of Operators Symbols
Concatenate & Replicate
Unary ! ~ & ^ ^~ |
Arithmetic * / % + -
Logical shift << >>
Relational < <= > >=

Equality == != === !==

Binary bit-wise & ^ ^~ |
Binary logical && ||
Conditional ?:
Logical Operators
 AND - &&,OR-|| , NOT - !
 Evaluated to single bit value

module logical_op();
reg[2:0] a,b,c;
reg x,y,z;
initia
begin
a=5,b=3’b111,c=x; Simulation
x=a&&b; result:
Y=a&&c; x=1;y=x,z=0
Z=b&&0;
$display(“x=%b,y=%b,z=%b”,xyz);
End
endmodule
Bitwise Operators
module bitwise_op();
reg[2:0] a,b,c;
 AND[&]
reg x,y,z;
 OR[|] initial
 XOR[^] begin
 NEGATION[~] a=5,b=3’b111,c=x;
 XNOR[~^ or^~] x=a&b;
Y=a&c;
Z=b&1;
$display(“x=%b,y=%b,z=%b”,xyz);
end;
X= 1 0 1 endmodule
& & &
Y= 1 1 1
Simulation Result:
X=101 ,y =xxx , z=001
Z= 1 0 1
Reduction Operators
 It contains only one operand and one operator,
 This is unary Operator
 AND[&],OR[|],XOR[^],XNOR[~^ or^~],NAND[~&]

module reduction_op();
Reg[3:0] a,b;
reg y,z;
Simulation Result: initial begin
y =1 , z=0 a=4’b0110;b=4’b1000;
Y=~&b;
Z=^a;
$display(“y=%b,z=%b”,y,z);
end
endmodule
 Shift Operators
 Shift Right [>>] ,Shift Left [<<]
 Result is same length as operand
Logical Shift (>>,<<) module shift_op();
reg[2:0] a,b,x,y,z;
 Fill the vacated bit positions with zeroes
initial begin
Arithmetic Shift Operators (<<<,>>>) a=4’b0110,b=4’b1100;
The arithmetic right shift fill the vacated x=a<<1;
bit positions with zeroes If the result Y=b>>2;
type is unsigned. Z=a>>>1;
$display(“x=%b,y=%b,z=%b”,
X,y,z);
Fill the vacated bit positions with the end
value of the MSB bit the left operand if endmodule
The result type is signed
 Concatenation Operators
module concat_op();
reg a;
 It is the joining together of bits Reg[2:0] b,c;
Resulting from two or more expressions Reg[7:0] x,y,z;
 Operands must be sized initial begin
a=1’b1,b=3’b100;c=3’b110;
x={a,b,c};
module concat_op();
y={a,2’b01,a};
reg a;
Simulation Result: z={x[1:0],b[2:1],c};
Reg[2:0] b,c;
x= 11_100_101101 $display(“x=%b,y=%b,z=%b”,
Reg[10:0] x;
X,y,z);
initial begin
end
a=1’b1,b=3’b100;c=3’b101;
endmodule
X={2{a},b,2{c}};
$display(“x=%b”,x);
end Simulation Result:
endmodule x= 1_100_110,y=100_01_1,z=10_10_110
Relational Operators
 > ,>= ,< ,<=
 It evaluates to a single bit value 0(false) or
 1(true)
a=4;b=3;
a=4;b=3; x=4’b1000;y=2’b11;z=4’b1x1x
x=4’b1000;y=2’b11;
x>=y //evaluates to logical 1 a<b //evaluates to logical 0
x<=y //evaluates to logical 0 a>b //evaluates to logical 1

x>=y //evaluates to logical 1

x<=y //evaluates to logical 0
x>=z //evaluates to logical x;
Equality Operators

Logical == != Case ===

!==
LOGICAL EQUALITY CASE EQUALITY

a=4’b1x0z;b=4’b1x0z; a=4’b1x0z;b=4’b1x0z;

a==b//evaluates to x a===b//evaluates to 1
a!=b//evaluates to x a!==b//evaluates to 0
Conditional Operators

 Syntax:
condition_expression ? true_expression : false_expression
reg[2:0] a,b,c,y,z;
false_exp
a=4’b1010;b=4’b0010;c=4’b1110;
out y=(&c)?a:b; //y gets b
z=c?a:b; //z gets a(c not equal to )

true_exp

condition_exp
Arithmetic operators
module arith_op();
reg[3:]a,b,c;
 Multiplication[*] iteger d,e;
 Division[/] reg[3:0]x,y,z;
integer k,l,m;
 Substract [-] initial
begin
 Add[+] a=4’b0010;b=4’b0011;c=4’b101x;
 Modulus[%] d-=3; e=8;
x=a*b; //evaluates to 0110
 Expensive on gates y=a+b; //evaluates to 0101
z=b-a; //evaluates to 0001
k=c*a; //evaluates to x
l=e/d //evaluates to 2,fraction is truncated
m=e%d; //evaluates to 2
end
endmodule
if else statement

 The if construct checks assignment1

a specific condition and
decides execution
condition
based on the result.
always@(.....);
begin
assignment1;
if(condition)
begin//alternative1 Assignment 2 Assignment 3
assignment2;
end
else
begin //alternative 2
assignment3; Assignment 4
end
Assignment4;
end
Multiway Branching
 If statements imply If sel[0]=0 then z will
be assigned a. none of the other
priority. assignments will be executed
Assignment1
always@(sel)
yes begin
condition if(sel[0]==0)
z=a;
else if(sel[2:1]==2’b01)
yes Assignment 2
condition z=b;
else if(sel[2:1]==2’b10)
Assignment 3
z=c;
Assignment 4 else if(sel[2:1]==2’b11)
z=d
else
Assignment 5 z=a;
end
Case Statement
 Multiway decision statement that tests Syntax:
whether an expression matches one case(expression)
of a number of other expression and case_item1:statement1;
branches accordingly case_item2:statement 2;
Possible values for
the case expression ………………
default:default_statement;
Optional default statement endcase
reg[0:3] a,b,c,z; reg[0:3] a,b,c,z;
integer x; integer x;
always@(a,b,c,x) always@(a,b,c,x)
case(x) case(x)
Covers all other
0:z=a; 0,2:z=a; Covers multiple
Possible values
1:z=b; 1,3:z=b; conditions
default :z=c; default :z=c;
endcase endcase
Looping Statements
for loop
 Its execution is a 3 step process as follows

Initialize a variable that reg[2:0]mem[7:0];

controls the number of loops integer I;
executed. reg read_mem;
Evaluates an expression if the initial
result is zero, the loop exits, begin
and if it is not zero, the for-loop for(i=0;i<10;i=i+1)
executes its associated $display(“data at location”,
statements(s) and then perform i,”is”,mem[i]);
step c. end
Executes an assignment,
normally modifies the value of
the loop control variable, then
repeats step b.
Looping Statements
While Loops Example counts the number
of logic 1 value in rega
 Executes a statement until
beginreg[7:0] tempreg;
an expression becomes
count =0;
false. While tempreg
tempreg = rega;
 If the expression starts out is not all 0
while(tempreg)
false , the statement does begin
not executes at all. th
if(tempreg[0]) If 0 bit is 1,count
is incremented
count = count+1;
tempreg = tempreg>>1;
end
end
tempreg is shifted
Right by one place
 Functions
 Functions can enable other syntax:function[width]function_name
functions (input input_args);
begin
but not another task. function_body;
 Functions always execute in end
endfunction
zero simulation time.
 Functions must not include reg[31:0]address;
Function declared
delay, timing control statements. Function parity_cal;
Input[31:0]data;
 Functions must have at least one Begin
input argument. Parity_cal=~data;
 Functions return a single value. End
They cannot have output or in end function
Function called
out arguments. always@(address)
Parity_reg=parity_cal(address);