Control unit-COA

RCA104
Microprogrammed Control

MICROPROGRAMMED CONTROL

• Control Memory

• Sequencing Microinstructions

• Microprogram Example

• Design of Control Unit

• Microinstruction Format

• Nanostorage and Nanoprogram

Microprogrammed Control Implementation of Control Unit

COMPARISON OF CONTROL UNIT IMPLEMENTATIONS

Control Unit Implementation
Combinational Logic Circuits (Hard-wired)

Control Data
Memory IR Status F/Fs

Control Unit's State

Timing State
Combinational Control CPU
Logic Circuits Points
Ins. Cycle State

Microprogram

M Control Data
e
m
o IR Status F/Fs
r
y

C Control C
Next Address Storage C
S S D P CPU
Generation A (-program D
Logic s
R memory) R }
Microprogrammed Control

TERMINOLOGY
Microprogram
- Program stored in memory that generates all the control signals required
to execute the instruction set correctly
- Consists of microinstructions

Microinstruction
- Contains a control word and a sequencing word
Control Word - All the control information required for one clock cycle
Sequencing Word - Information needed to decide
the next microinstruction address
- Vocabulary to write a microprogram

Control Memory(Control Storage: CS)

- Storage in the microprogrammed control unit to store the microprogram
Writeable Control Memory(Writeable Control Storage:WCS)
- CS whose contents can be modified
-> Allows the microprogram can be changed
-> Instruction set can be changed or modified
Dynamic Microprogramming
- Computer system whose control unit is implemented with
a microprogram in WCS
- Microprogram can be changed by a systems programmer or a user
Microprogrammed Control

TERMINOLOGY

Sequencer (Microprogram Sequencer)

A Microprogram Control Unit that determines

the Microinstruction Address to be executed
in the next clock cycle

- In-line Sequencing
- Branch
- Conditional Branch
- Subroutine
- Loop
- Instruction OP-code mapping
Microprogrammed Control Sequencing

MICROINSTRUCTION SEQUENCING
Instruction code

Mapping
logic
Status MUX Multiplexers
bits Branchselect
logic
Subroutine
register
Control address register (SBR)
(CAR)
Incrementer

Control memory (ROM)

select a status
bit
Microoperations
Branch address

Sequencing Capabilities Required in a Control Storage

- Incrementing of the control address register
- Unconditional and conditional branches
- A mapping process from the bits of the machine
instruction to an address for control memory
- A facility for subroutine call and return
Microprogrammed Control Sequencing

CONDITIONAL BRANCH

Load address
Control address register

Increment

MUX
Control memory

...
Status bits
(condition)

Condition select Micro-operations

Next address

Conditional Branch

If Condition is true, then Branch (address from

the next address field of the current microinstruction)
else Fall Through
Conditions to Test: O(overflow), N(negative),
Z(zero), C(carry), etc.
Unconditional Branch
Fixing the value of one status bit at the input of the multiplexer to 1
Microprogrammed Control Sequencing

MAPPING OF INSTRUCTIONS
Direct Mapping Address
OP-codes of Instructions 0000 ADD Routine
0001 AND Routine
ADD 0000 0010
. LDA Routine
AND 0001 . 0011 STA Routine
LDA 0010 . 0100 BUN Routine
STA 0011 Control
BUN 0100 Storage

Mapping
10 xxxx 010
Bits Address
10 0000 010 ADD Routine

10 0001 010 AND Routine

10 0010 010 LDA Routine

10 0011 010 STA Routine

10 0100 010 BUN Routine

Microprogrammed Control Sequencing

MAPPING OF INSTRUCTIONS TO MICROROUTINES

Mapping from the OP-code of an instruction to the

address of the Microinstruction which is the starting
microinstruction of its execution microprogram
Machine OP-code
Instruction 1 0 1 1 Address

Mapping bits 0 x x x x 0 0
Microinstruction
address 0 1 0 1 1 0 0

Mapping function implemented by ROM or PLA

OP-code

Mapping memory
(ROM or PLA)

Control address register

Control Memory
Microprogrammed Control Microprogram

MICROPROGRAM EXAMPLE
Computer Configuration

MUX
10 0
AR
Address Memory
10 0 2048 x 16
PC

MUX

15 0
6 0 6 0 DR
SBR CAR

Control memory Arithmetic

128 x 20 logic and
shift unit
Control unit
15 0
AC
Microprogrammed Control Microprogram

MACHINE INSTRUCTION FORMAT

Machine instruction format

15 14 11 10 0
I Opcode Address

Sample machine instructions

Symbol OP-code Description
EA is the effective address
ADD 0000 AC  AC + M[EA]
BRANCH 0001 if (AC < 0) then (PC  EA)
STORE 0010 M[EA]  AC
EXCHANGE 0011 AC  M[EA], M[EA]  AC

Microinstruction Format
3 3 3 2 2 7
F1 F2 F3 CD BR AD

F1, F2, F3: Microoperation fields

CD: Condition for branching
BR: Branch field
AD: Address field
Microprogrammed Control Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - F1,F2,F3

F1 Microoperation Symbol F2 Microoperation Symbol

000 None NOP 000 None NOP
001 AC  AC + DR ADD 001 AC  AC - DR SUB
010 AC  0 CLRAC 010 AC  AC  DR OR
011 AC  AC + 1 INCAC 011 AC  AC  DR AND
100 AC  DR DRTAC 100 DR  M[AR] READ
101 AR  DR(0-10) DRTAR 101 DR  AC ACTDR
110 AR  PC PCTAR 110 DR  DR + 1 INCDR
111 M[AR]  DR WRITE 111 DR(0-10)  PC PCTDR

F3 Microoperation Symbol
000 None NOP
001 AC  AC  DR XOR
010 AC  AC’ COM
011 AC  shl AC SHL
100 AC  shr AC SHR
101 PC  PC + 1 INCPC
110 PC  AR ARTPC
111 Reserved
Microprogrammed Control Microprogram

MICROINSTRUCTION FIELD DESCRIPTIONS - CD, BR

CD Condition Symbol Comments

00 Always = 1 U Unconditional branch
01 DR(15) I Indirect address bit
10 AC(15) S Sign bit of AC
11 AC = 0 Z Zero value in AC

BR Symbol Function
00 JMP CAR  AD if condition = 1
CAR  CAR + 1 if condition = 0
01 CALL CAR  AD, SBR  CAR + 1 if condition = 1
CAR  CAR + 1 if condition = 0
10 RET CAR  SBR (Return from subroutine)
11 MAP CAR(2-5)  DR(11-14), CAR(0,1,6)  0
Microprogrammed Control Microprogram

SYMBOLIC MICROINSTRUCTIONS
• Symbols are used in microinstructions as in assembly language
• A symbolic microprogram can be translated into its binary equivalent by a
microprogram assembler.

Sample Format
five fields: label; micro-ops; CD; BR; AD

Label: may be empty or may specify a symbolic

address terminated with a colon

Micro-ops: consists of one, two, or three symbols

separated by commas

CD: one of {U, I, S, Z}, where U: Unconditional Branch

I: Indirect address bit
S: Sign of AC
Z: Zero value in AC

BR: one of {JMP, CALL, RET, MAP}

AD: one of {Symbolic address, NEXT, empty}

Microprogrammed Control Microprogram

SYMBOLIC MICROPROGRAM - FETCH ROUTINE

During FETCH, Read an instruction from memory

and decode the instruction and update PC

Sequence of microoperations in the fetch cycle:

AR  PC
DR  M[AR], PC  PC + 1
AR  DR(0-10), CAR(2-5)  DR(11-14), CAR(0,1,6)  0

Symbolic microprogram for the fetch cycle:

ORG 64
FETCH: PCTAR U JMP NEXT
READ, INCPC U JMP NEXT
DRTAR U MAP

Binary equivalents translated by an assembler

Binary
address F1 F2 F3 CD BR AD
1000000 110 000 000 00 00 1000001
1000001 000 100 101 00 00 1000010
1000010 101 000 000 00 11 0000000
Microprogrammed Control Microprogram

SYMBOLIC MICROPROGRAM
• Control Storage: 128 20-bit words
• The first 64 words: Routines for the 16 machine instructions
• The last 64 words: Used for other purpose (e.g., fetch routine and other subroutines)
• Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are
0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ..., 60

Partial Symbolic Microprogram

Label Microops CD BR AD
ORG 0
ADD: NOP I CALL INDRCT
READ U JMP NEXT
ADD U JMP FETCH

ORG 4
BRANCH: NOP S JMP OVER
NOP U JMP FETCH
OVER: NOP I CALL INDRCT
ARTPC U JMP FETCH

ORG 8
STORE: NOP I CALL INDRCT
ACTDR U JMP NEXT
WRITE U JMP FETCH

ORG 12
Microprogrammed Control Microprogram

BINARY MICROPROGRAM
Address Binary Microinstruction
Micro Routine Decimal Binary F1 F2 F3 CD BR AD
ADD 0 0000000 000 000 000 01 01 1000011
1 0000001 000 100 000 00 00 0000010
2 0000010 001 000 000 00 00 1000000
3 0000011 000 000 000 00 00 1000000
BRANCH 4 0000100 000 000 000 10 00 0000110
5 0000101 000 000 000 00 00 1000000
6 0000110 000 000 000 01 01 1000011
7 0000111 000 000 110 00 00 1000000
STORE 8 0001000 000 000 000 01 01 1000011
9 0001001 000 101 000 00 00 0001010
10 0001010 111 000 000 00 00 1000000
11 0001011 000 000 000 00 00 1000000
EXCHANGE 12 0001100 000 000 000 01 01 1000011
13 0001101 001 000 000 00 00 0001110
14 0001110 100 101 000 00 00 0001111
15 0001111 111 000 000 00 00 1000000

FETCH 64 1000000 110 000 000 00 00 1000001

65 1000001 000 100 101 00 00 1000010
66 1000010 101 000 000 00 11 0000000
INDRCT 67 1000011 000 100 000 00 00 1000100
68 1000100 101 000 000 00 10 0000000

This microprogram can be implemented using ROM

Microprogrammed Control Design of Control Unit
DESIGN OF CONTROL UNIT
- DECODING ALU CONTROL INFORMATION -

microoperation fields
F1 F2 F3

3 x 8 decoder 3 x 8 decoder 3 x 8 decoder

76 54 3 21 0 7 6 54 3 21 0 76 54 321 0

AND
ADD AC
Arithmetic
logic and
DRTAC shift unit DR

From From
PCTAR

DRTAR

PC DR(0-10) Load
AC

Select 0 1
Multiplexers

Load Clock
AR

Decoding of Microoperation Fields

Microprogrammed Control Design of Control Unit
MICROPROGRAM SEQUENCER
- NEXT MICROINSTRUCTION ADDRESS LOGIC -
Branch, CALL Address
External RETURN form Subroutine
(MAP)
In-Line
S1 S0 Address Source
00 CAR + 1, In-Line 3 2 1 0
S MUX1 L
01 SBR RETURN SBR Subroutine
10 CS(AD), Branch or CALL S1 CALL
Address 0
11 MAP source
selection
Incrementer

Clock CAR

Control Storage

MUX-1 selects an address from one of four sources and routes it into a CAR

- In-Line Sequencing  CAR + 1

- Branch, Subroutine Call  CS(AD)
- Return from Subroutine  Output of SBR
- New Machine instruction  MAP
Microprogrammed Control Design of Control Unit
MICROPROGRAM SEQUENCER
- CONDITION AND BRANCH CONTROL -

1 L L(load SBR with PC) for

From I MUX2 Test
CPU SZ
T
Input subroutine Call
Select BR field I0 logic
of CS I1
S0 for next address
S1 selection
CD Field of CS

Input Logic
I1I0T Meaning Source of Address S1S0 L

000 In-Line CAR+1 00 0

001 JMP CS(AD) 01 0
010 In-Line CAR+1 00 0
011 CALL CS(AD) and SBR <- CAR+1 01 1
10x RET SBR 10 0
11x MAP DR(11-14) 11 0
S1 = I 1
S0 = I1I0 + I1’T
L = I1’I0T
Microprogrammed Control Design of Control Unit

MICROPROGRAM SEQUENCER
External
(MAP)

L
I0 3 2 1 0
Input Load
I1 S1 MUX1 SBR
logic
T S0

1 Incrementer
I MUX2 Test
S
Z Select
Clock CAR

Control memory

Microops CD BR AD
... ...
Microprogrammed Control Microinstruction Format

MICROINSTRUCTION FORMAT

Information in a Microinstruction
- Control Information
- Sequencing Information
- Constant
Information which is useful when feeding into the system

These information needs to be organized in some way for

- Efficient use of the microinstruction bits
- Fast decoding

Field Encoding

- Encoding the microinstruction bits

- Encoding slows down the execution speed
due to the decoding delay
- Encoding also reduces the flexibility due to
the decoding hardware
Microprogrammed Control Microinstruction Format
HORIZONTAL AND VERTICAL
MICROINSTRUCTION FORMAT
Horizontal Microinstructions
Each bit directly controls each micro-operation or each control point
Horizontal implies a long microinstruction word
Advantages: Can control a variety of components operating in parallel.
--> Advantage of efficient hardware utilization
Disadvantages: Control word bits are not fully utilized
--> CS becomes large --> Costly
Vertical Microinstructions
A microinstruction format that is not horizontal
Vertical implies a short microinstruction word
Encoded Microinstruction fields
--> Needs decoding circuits for one or two levels of decoding
One-level decoding Two-level decoding

Field A Field B
Field A Field B
2 bits 6 bits
2 bits 3 bits

2x4 6 x 64
2x4 3x8 Decoder Decoder
Decoder Decoder

Decoder and
1 of 4 1 of 8 selection logic
Microprogrammed Control Control Storage Hierarchy

NANOSTORAGE AND NANOINSTRUCTION

The decoder circuits in a vertical microprogram
storage organization can be replaced by a ROM
=> Two levels of control storage
First level - Control Storage
Second level - Nano Storage

Two-level microprogram

First level
-Vertical format Microprogram
Second level
-Horizontal format Nanoprogram
- Interprets the microinstruction fields, thus converts a vertical
microinstruction format into a horizontal
nanoinstruction format.

Usually, the microprogram consists of a large number of short

microinstructions, while the nanoprogram contains fewer words with longer
nanoinstructions.
Microprogrammed Control Control Storage Hierarchy

TWO-LEVEL MICROPROGRAMMING - EXAMPLE

* Microprogram: 2048 microinstructions of 200 bits each
* With 1-Level Control Storage: 2048 x 200 = 409,600 bits
* Assumption:
256 distinct microinstructions among 2048
* With 2-Level Control Storage:
Nano Storage: 256 x 200 bits to store 256 distinct nanoinstructions
Control storage: 2048 x 8 bits
To address 256 nano storage locations 8 bits are needed
* Total 1-Level control storage: 409,600 bits
Total 2-Level control storage: 67,584 bits (256 x 200 + 2048 x 8)
Control address register

11 bits

Control memory
2048 x 8

Microinstruction (8 bits)
Nanomemory address

Nanomemory
256 x 200

Nanoinstructions (200 bits)

Central Processing Unit

Overview

• Instruction Set Processor (ISP)

• Central Processing Unit (CPU)
• A typical computing task consists of a series of
steps specified by a sequence of machine
instructions that constitute a program.
• An instruction is executed by carrying out a
sequence of more rudimentary operations.
Central Processing Unit

Fundamental Concepts
• Processor fetches one instruction at a time and perform
the operation specified.
• Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
• Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
• Instruction Register (IR)
Central Processing Unit

Executing an Instruction
• Fetch the contents of the memory location pointed to by
the PC. The contents of this location are loaded into the
IR (fetch phase).
IR ← [[PC]]
• Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC ← [PC] + 4
• Carry out the actions specified by the instruction in the IR
(execution phase).
Central Processing Unit
Internal processor
bus

Processor Organization
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines
Carry -in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

MDR HAS TWO

INPUTS AND
TWO OUTPUTS

Datapath

Textbook Page 413

Central Processing Unit

Executing an Instruction

• Transfer a word of data from one processor

register to another or to the ALU.
• Perform an arithmetic or a logic operation and
store the result in a processor register.
• Fetch the contents of a given memory location
and load them into a processor register.
• Store a word of data from a processor register
into a given memory location.
Central Processing Unit

Register Transfers
Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Central Processing Unit
Bus

Ri in
Clock
D Q

Figure 7.3. Input and outputating

Riout

g for one gister

re bit.
Register Transfers
• All operations and data transfers are controlled by the processor clock.

Figure 7.3. Input and output gating for one register bit.
Central Processing Unit

Performing an Arithmetic or Logic

Operation
• The ALU is a combinational circuit that has no internal
storage.
• ALU gets the two operands from MUX and bus. The
result is temporarily stored in register Z.
• What is the sequence of operations to add the contents
of register R1 to those of R2 and store the result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
Central Processing Unit

Fetching a Word from Memory

Memory -bus
data lines MDRoutE

MDR inE
MDR
MDRout

MDRin
Internal processor
bus

Figure 7.4. Connection and control signals for

gister
re MDR.

• Address into MAR; issue Read operation; data into MDR.

Figure 7.4. Connection and control signals for register MDR.

Central Processing Unit

Fetching a Word from Memory

• The response time of each memory access varies (cache
miss, memory-mapped I/O,…).
• To accommodate this, the processor waits until it
receives an indication that the requested operation has
been completed (Memory-Function-Completed, MFC).
• Move (R1), R2
 MAR ← [R1]
 Start a Read operation on the memory bus
 Wait for the MFC response from the memory
 Load MDR from the memory bus
 R2 ← [MDR]
 MFC

Central Processing Unit MDR out

Figure 7.5. Timing of a memory Read operation.

Timing
MAR ← [R1]
Assume MAR
is always available
on the address lines
of the memory bus. Start a Read operation on the memory bus

Wait for the MFC response from the memory

Load MDR from the memory bus

R2 ← [MDR]
Central Processing Unit

Execution of a Complete
Instruction
• Add (R3), R1
• Fetch the instruction
• Fetch the first operand (the contents of the
memory location pointed to by R3)
• Perform the addition
• Load the result into R1
Central Processing Unit

Architecture
Internal processor
bus
Riin

Ri

Riout

Yin

Constant 4

Select MUX

A B
ALU

Zin

Zout

Figure 7.2. Input and output gating for the registers in Figure 7.1.
Central Processing Unit
Internal processor
bus

Execution of a Complete
Control signals

PC

Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Step Action Y
Constant 4 R0

1 PCout , MAR in , Read, Select4,A dd, Zin Select MUX

2 Zout , PCin , Y in , WMF C

Add
A B
3 MDR out , IR in ALU Sub R n - 1
control ALU
4 R3out , MAR in , Read lines
Carry -in
XOR TEMP
5 R1out , Y in , WMF C
6 MDR out , SelectY,Add, Zin Z

7 Zout , R1 in , End

Figure 7.1. Single-bus organization of the datapath inside a processor.

Instruction
Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

Add (R3), R1
Central Processing Unit

Execution of Branch Instructions

• A branch instruction replaces the contents of

PC with the branch target address, which is
usually obtained by adding an offset X given in
the branch instruction.
• The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
• Conditional branch
Central Processing Unit

Execution of Branch Instructions

Step Action

1 PCout , MAR in , Read, Select4,Add, Z in

2 Zout , PCin , Yin , WMF C
3 MDR out , IR in
4 Offset-field-of-IRout, Add, Z in
5 Z out , PCin , End

Figure 7.7. Control sequence for an unconditional branch instruction.

Central Processing Unit

Multiple-Bus Organization
Bus A Bus B Bus C

Incrementer

PC

Register
f ile

Constant 4

MUX
A

ALU R

Instruction
decoder

IR

MDR

MAR

Memory bus Address

data lines lines

Figure 7.8. Three-bus organization of the datapath.

Central Processing Unit

Multiple-Bus Organization
• Add R4, R5, R6

Step Action

1 PCout, R=B, MAR in , Read, IncPC

2 WMFC
3 MDR outB , R=B, IR in
4 R4outA , R5outB , SelectA, Add, R6in , End

Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,

for the three-bus organization in Figure 7.8.
Central Processing Unit
Internal processor
bus
Control signals

PC

Quiz
Instruction
Address
decoder and
lines
MAR control logic

Memory
bus

MDR
Data
lines IR

Y
Constant 4 R0

Select MUX

Add
A B
ALU Sub R n - 1
control ALU
lines
Carry -in
XOR TEMP

Figure 7.1. Single-bus organization of the datapath inside a processor.

• What is the control

sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
Central Processing Unit

Control Unit Organization

CLK Control step
Clock counter

External
inputs
Decoder/
IR
encoder
Condition
codes

Control signals

Figure 7.10. Control unit organization.

Central Processing Unit Clock
CLK
Control step
counter
Reset

Step decoder

T 1 T2 Tn

Detailed Block Description

INS1
External
INS2 inputs
Instruction
IR Encoder
decoder
Condition
codes
INSm

Run End

Control signals

Figure 7.11. Separation of the decoding and encoding functions.

Central Processing Unit

Generating Zin

• Zin = T1 + T6 • ADD + T4 • BR + …
Branch Add

T T
4 6

T
1

Figure 7.12. Generation of the Zin control signal for the processor in Figure 7.1.
Central Processing Unit

Generating End
Branch<0
Add Branch
N N

T7 T5 T4 T5

End

Figure 7.13. Generation of the End control signal.

• End = T7 • ADD + T5 • BR + (T5 • N + T4 • N) • BRN +…

Central Processing Unit
Instruction Integer Floating-point
unit unit unit

A Complete Processor
Instruction Data
cache cache

Bus interface
Processor

Sy stem us
b

Main Input/
memory Output

Figure 7.14. Block diagram of a complete processor

.
Microprogrammed Control

Overview

MDRout

WMFC
MAR in

Select
Read
PCout

R1out

R3out
Micro -

End
PCin

R1in
Add

Z out
IRin
Yin

Zin
instruction

1 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0
2 1 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
3 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0

•
4 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0

Control signals are generated by a program similar to machine language

5 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0
6 0 0 0 0 1 0 0 0 1 1 0 0 0 0 0 0
7 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1

Figure 7.15 An example of microinstructions for Figure 7.6.

programs.
• Control Word (CW); microroutine; microinstruction
Microprogrammed Control

Step

1
2
3
4
5
6
7
Action

PCout , MAR in , Read, Select4,A dd, Zin

Zout , PCin , Y in , WMF C
MDR out , IR in
R3out , MAR in , Read
R1out , Y in , WMF C
MDR out , SelectY,Add, Zin
Zout , R1 in , End

Figure 7.6. Control sequencefor executionof the instruction Add (R3),R1.

Overview
Microprogrammed Control
Starting
IR address

Overview
generator

Clock PC

Control
store CW

Figure 7.16. Basic organization of a microprogrammed control unit.

• Control store

One function
cannot be carried
out by this simple
organization.
Microprogrammed Control

Overview
• The previous organization cannot handle the situation when the control unit is
required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
• Use conditional branch microinstruction.
Address Microinstruction

0 PCout , MAR in , Read, Select4,Add, Z in

1 Zout , PCin , Y in , WMFC
2 MDRout , IR in
3 Branch to starting addressof appropriatemicroroutine
. ... .. ... ... .. ... .. ... ... .. ... ... .. ... .. ... ... .. ... .. ... ... .. ... ..
25 If N=0, then branch to microinstruction0
26 Offset-field-of-IRout , SelectY, Add, Z in
27 Zout , PCin , End

Figure 7.17. Microroutine for the instruction Branch<0.

Microprogrammed Control

Overview
External
inputs

Starting and
branch address Condition
IR codes
generator

Clock PC

Control
store CW

Figure 7.18. Organization of the control unit to allow

conditional branching in the microprogram.
Microprogrammed Control

Microinstructions

• A straightforward way to structure

microinstructions is to assign one bit position
to each control signal.
• However, this is very inefficient.
• The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
• All mutually exclusive signals are placed in the
same group in binary coding.
Microprogrammed Control
Microinstruction

F1 F2 F3 F4 F5

Partial Format for the

F1 (4 bits) F2 (3 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)

0000: No transf er 000: No transf er000: No transf er 0000: Add 00: No action
0001: PCout 001: PCin 001: MARin 0001: Sub 01: Read
0010: MDRout 010: IRin 010: MDRin 10: Write
0011: Zout 011: Zin 011: TEMPin
0100: R0out 100: R0in 100: Yin 1111: XOR
0101: R1out 101: R1in
0110: R2 110: R2in 16 ALU
out f unctions
0111: R3out 111: R3in
1010: TEMPout
1011: Of f set
out

F6 F7 F8

F6 (1 bit) F7 (1 bit) F8 (1 bit)

0: SelectY 0: No action 0: Continue

1: Select4 1: WMFC 1: End

Figure 7.19. An example of a partial format for field-encoded microinstructions.

Microinstructions

What is the price paid for

this scheme?
Microprogrammed Control

Further Improvement

• Enumerate the patterns of required signals in

all possible microinstructions. Each
meaningful combination of active control
signals can then be assigned a distinct code.
• Vertical organization
• Horizontal organization
Microprogrammed Control

Microprogram Sequencing
• If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a μPC governs the sequencing would be
efficient.
• However, two disadvantages:
 Having a separate microroutine for each machine instruction results in a
large total number of microinstructions and a large control store.
 Longer execution time because it takes more time to carry out the
required branches.
• Example: Add src, Rdst
• Four addressing modes: register, autoincrement,
autodecrement, and indexed (with indirect forms).
Microprogrammed Control

- Bit-ORing
- Wide-Branch Addressing
- WMFC
Microprogrammed Control
Mode
Contents of IR OP code 0 1 0 Rsrc Rdst
1110 87 43 0

Address Microinstruction
(octal)

000 PCout, MARin, Read, Select, Add, Zin

4
001 Zout, PCin, Yin, WMFC
002 MDRout, IRin
003
Branch {PC101 (from Instruction decoder);
PC5,4 [IR10,9]; PC3 [IR 10]  [IR9]  [IR8]}
121 Rsrcout , MARin , Read, Select4, Add,inZ
122 Zout, Rsrcin
123 Branch {PC 170;PC0  [IR8]}, WMFC
170 MDRout, MARin, Read, WMFC
171 MDRout, Yin
172 Rdstout , SelectY
, Add, Zin
173 Zout, Rdstin, End

Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.

Note:Microinstruction at location 170 is not executed for this addressing mode.
Microprogrammed Control

Microinstructions with Next-

Address Field
• The microprogram we discussed requires several branch
microinstructions, which perform no useful operation in
the datapath.
• A powerful alternative approach is to include an address
field as a part of every microinstruction to indicate the
location of the next microinstruction to be fetched.
• Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
• Cons: additional bits for the address field (around 1/6)
Microprogrammed Control
IR

External Condition

Microinstructions with Next-

Inputs codes

Decoding circuits

A R

Control store

Next address I R

Microinstruction decoder

Control signals

Figure 7.22. Microinstruction-sequencing organization.

Address Field
Microprogrammed Control
Microprogrammed Control
Octal
address F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10

Implementation of the
000 0 0 0 0 0 0 0 1 0 0 1 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
001 0 0 0 0 0 0 1 0 0 1 1 00 1 1 0 0 0 0 0 0 00 0 1 0 0 0
002 0 0 0 0 0 0 1 1 0 1 0 01 0 0 0 0 0 0 0 0 00 0 0 0 0 0
003 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 00 0 0 1 1 0

121 0 1 0 1 0 0 1 0 1 0 0 01 1 0 0 1 0 0 0 0 01 1 0 0 0 0
122 0 1 1 1 1 0 0 0 0 1 1 10 0 0 0 0 0 0 0 0 00 0 1 0 0 1

170 0 1 1 1 1 0 0 1 0 1 0 00 0 0 0 1 0 0 0 0 01 0 1 0 0 0
171 0 1 1 1 1 0 1 0 0 1 0 00 0 1 0 0 0 0 0 0 00 0 0 0 0 0
172 0 1 1 1 1 0 1 1 1 0 1 01 1 0 0 0 0 0 0 0 00 0 0 0 0 0
173 0 0 0 0 0 0 0 0 0 1 1 10 1 0 0 0 0 0 0 0 00 0 0 0 0 0

Figure 7.24. Implementation of the microroutine of Figure 7.21 using a

next-microinstruction address field.
(See Figure 7.23 for encoded signals.)

Microroutine
 Rdstin
Microinstruction
decoder
Rsrcout

Microprogrammed Control
Rsrcin

Other control signals

Figure 7.25. Some details of the control-signal-generating circuitry.

Microprogrammed Control

bit-ORing