CHAPTER 1:

DIGITAL IC DESIGN
OVERVIEW
BEEC4844
CONTENTS

 Introduction to Digital IC Design

 Digital IC Design flow
 Basic Timing Analysis
 Design & Develop using Hardware Description Language
 Challenges
Introduction to Digital IC Design

 Integrated Circuits (IC):

 Integration of set of electronic circuits on a very tiny piece of
semiconductor device.

 Digital IC Circuits:
 IC which receive, manipulate and produced digital or discrete signals.

 In VLSI course, you have learned that:

 IC are made of MOS transistors
 Going through a series of lithography process
 Design  fabrication  packaging
DIGITAL IC DESIGN APPLICATIONS

Microprocessor & Microcontroller

Graphics Processor

Memory

Field-Programmable Gate Array

And many more….

DIGITAL VS ANALOG IC

 An IC can be either digital / analog / mixed signal IC

DIGITAL ANALOG
Accept and Output digital / discrete Accept and output analog / continuous
signals signal
Works with states of voltages (low or high) Works by varying voltages
Generally high gate count, high density Generally contains lower number of
and high speed transistors, lower density
Example: Example:
microP, memory, image processor Amplifier, power management, PLL
MOTIVATION OF USING DIGITAL SYSTEM

 Digital data present high-degree of manipulation:

 Image editing/processing/enhancement
 Audio effect/enhancement
 Easily corrected, compressed and multiplexed
 Scalability
 Immunity to noise
 Suitable for high-speed, low-power and compact design
 DIGITAL IC DESIGN FLOW

System Architectural RTL

RTL Design
specification Design Verification

Physical Physical DFT

Synthesis
Verification Design Integration

Fabrication Packaging &

& Test Test
PHYSICAL DESIGN

 Consist of several stages:

 Partitioning
 Floor Planning
 Placement
 Clock Tree Synthesis
 Signal Routing
 Timing Closure
PHYSICAL DESIGN

 Partitioning
 Divide the chip into small blocks
 Separate functional blocks  easier placement & routing
 Can be done at RTL stage  divide design into sub-blocks

 Floorplanning
 Identifying structures that should be placed close together
 Allocating space based on requirements (area, performance etc.)
 Considering memory, IP cores used, routing possibilities
 To avoid wasting die area and routing congestion
PHYSICAL DESIGN

 Placement
 Placing gates on the die (chip)
 A few series of optimization: cells downsizing,
buffer insertion, net splitting, etc.

 Clock Tree Synthesis

 Goal: minimize skew and insertion delay
PHYSICAL DESIGN

 Signal routing
 Connect nodes via wires/metals
 Point of consideration: DRC, wire length, timing, etc.

 Timing closure
 Analysis on the circuit performance vs timing requirement
 Is the circuit can operate properly without any timing
violations?
INTRODUCTION TO IC TIMING ANALYSIS

 As we know, physical circuit certainly introduce delay:

 Each gate has their own gate or propagation delay
 It take several time for signal to propagate from one point to
another
 All these delays will be accumulated (snowball effect)

 Factors which introduce delay:

 Parasitic (resistance & capacitance)
 Materials
 Device size
DFF based Design

 Q becomes D after clock edge

 Setup time:
 Data cannot change between this point and
the clock edge

 Hold time:
 Data cannot change between the clock
edge and this point

 t_clock-Q:
 Delay on output (Q) changing from positive
clock edge
 SETUP TIME REQUIREMENT

 To avoid Setup time violation:

𝑻𝒄𝒍𝒌 ≥ 𝒕𝒑𝒄𝒒𝟏 + 𝒕𝒑𝒅𝒎𝒂𝒙 − 𝒕𝒔𝒌𝒆𝒘 + 𝒕𝒔
where
 𝒕𝒑𝒄𝒒𝟏 is clock-to-Q delay at DFF1
 𝒕𝒑𝒅𝒎𝒂𝒙 is the total maximum propagation
delay of the path
 𝒕𝒔𝒌𝒆𝒘 is the clock skew between DFF1 and
DFF2 (if negative, clock arrive at DFF2
earlier than DFF1)
 𝒕𝒔 is the setup time required
 SETUP TIME EXAMPLE

 Given the following critical path. 2 DFF with the same clock signal clk_sys with no skew.
Analyze the circuit and determine whether the setup time is violated or not. Given:
tpcq1 = 4ns, ts = 3 ns, and Fclk_sys = 10 MHz

 Determine the maximum clock frequency for this circuit.

HOLD TIME REQUIREMENT

 In order to avoid the hold time violation,

𝒕𝒉 + 𝒕𝒔𝒌𝒆𝒘 ≤ 𝒕𝒑𝒄𝒒𝟏 + 𝒕𝒑𝒅𝒎𝒊𝒏
Where:
 𝒕𝒉 is the hold time required
 𝒕𝒑𝒅𝒎𝒊𝒏 is the total min propagation delay
EFFECT OF TIMING VIOLATION

 D changes during setup and hold:

 tclock-Q longer than specified, or Q does not transition correctly

 Q changes in WRONG clock cycle (racethrough)

 FIXING SETUP AND HOLD TIME
VIOLATION
 Setup time violations are normally due to the signal being to slow.
 To fix Setup time violations:
 Reducing delays / buffers
 Adjusting cell position in layout
 Reduce clock frequency
 Use stronger cells which can drive path with high capacitance
 Hold time violations are normally due to data is too fast compared to the clock
speed
 To fix Hold time violations :
 By adding delays / buffers
 Use weaker cells  to ensure the transition time increase
 Maximum Operating Frequency

From this relation:

𝑻𝒄𝒍𝒌 ≥ 𝒕𝒑𝒄𝒒𝟏 + 𝒕𝒑𝒅𝒎𝒂𝒙 − 𝒕𝒔𝒌𝒆𝒘 + 𝒕𝒔

We know that the minimum period required for the circuit is

𝑻𝒄𝒍𝒌_𝒎𝒊𝒏 = 𝒕𝒑𝒄𝒒𝟏 + 𝒕𝒑𝒅𝒎𝒂𝒙 − 𝒕𝒔𝒌𝒆𝒘 + 𝒕𝒔
So,
𝟏
𝑭𝒎𝒂𝒙 =
𝑻𝒄𝒍𝒌_𝒎𝒊𝒏
Any decision to use higher clock frequency than Fmax will cause the
circuit not to function properly!
 OVERVIEW ON THE HARDWARE
DESCRIPTION LANGUAGE (HDL)

 Hardware Description Language (HDL) is used to describe a

digital system
 Architecture
 Functionality
 Connections
 Different HDL available:
 Verilog HDL (mostly used in US, Asia)
 VHDL (mainly used in Europe)
 VERILOG HDL

 Has three different abstraction levels:

 Behavioral level Example:
Testbench code
 Systems described by concurrent algorithms
for simulation
 Sequential, instructions executed one after the other.
 Structural realization is not important!
 Register-Transfer level (RTL)
 Describe circuits operations and the data transfers between registers
 Usually involving a clock (sequential circuits)
 Any synthesizable code is called RTL code!  to develop circuit design
 Gate level
Example:
 Logical links by using logic primitives (AND, OR, NOT, XOR, etc.) Netlist after
 Normally generated by synthesis tools synthesis
 VERILOG STRUCTURE
Module / design name
Inputs/outputs list

d q
Describe
symbol d_ff
clk q_bar

Architecture
Description d q
Describe internal
architecture
clk q_bar

Ending a module
Numbers in Verilog
 Radix
 Can be in bits, hexadecimal, integers or real
 A number can be written as: n’xyy...y
 n is the number of bits
 x is the type: binary (bits) or hexadecimal
 yy…y is the number to be written in binary/hexadecimal
 Example to write 14 in Verilog:
 4’b1110
Decimal Bits Hexadecimal
 4’hE
1 1’b1 1’h1
0 1’b0 1’h0
10 4’b1010 4’hA
22 5’b10100 5’h14
Numbers in Verilog
 Integer
 Can be sized or unsized (by default 32 bits)
 Examples:
integer Stored as
1 00000000000000000000000000000001
8'hAA 10101010
6'b10_0011 100011
'hF 00000000000000000000000000001111
Numbers in Verilog
 Signed / Unsigned Numbers

Number Description
32'hDEAD_BEEF Unsigned or signed positive number
-14'h1234 Signed negative number
Verilog Operators
 Arithmetic operators:
 +, -, *, /

 Relational operators:
Verilog Operators
 Equality operators:

 Logical operators:

 Bitwise operators:
Verilog Operators
 Shift operators:
 << left shift
 >> right shift

 Conditional operators (?:)

cond_expr ? true_expr : false_expr

Example:
// out takes data1 if sel is true (1), else data2
assign out = sel ? data1 : data2;
Simple Example (1)

&
|

OR
ADDER

A[3:0]
+ C[4:0]
B[3:0]
always block
always @ (sensitivity list)
begin
//assignments here
end

 always @ block always execute all the assignments within its body,
when the sensitivity list is triggered.
 Else, this block is in “sleep mode”.
always block examples:
always @ (posedge clock) always @ (x or y or sel)
begin begin
a <= a + 1; if (sel == 0)
end output <= x;
else
In this case, the a value will count output <= y;
up each time there are the rising end
edge of the clock signal.
In this case, the output value will
be updated only when there is an
event on x, y and/or sel signal.
Blocking and non-blocking assignments
 In always @ block, we can use either blocking (=) or non-blocking (<=)
assignments.
 Blocking:
 A statement must be executed first before proceeding to the next statement (like in C/C++)
 Useful for simulation testbench.
 Non-blocking:
 Assignments without blocking the procedural flow.
 All non-blocking statements are executed at the same time.
Blocking assignments
 Consider the following example:
always @ (posedge clock)
begin
b = a;
c = b;
end
 In this case, at the rising edge of the clock, c will become a!
Non-blocking assignments
 Consider the following example:
always @ (posedge clock)
begin
b <= a;
c <= b;
end
 In this case, at the rising edge of the clock, c will become old value of b!
ADDER IN RTL
In RTL, addition will be performed at each rising edge of the
clock  utilization of a register or flip-flop

A[3:0] C[4:0]
+
B[3:0]

clock

In this case (or RTL case), the output must be set to register (reg)!

always @ (event) block is used  to perform the instruction within its body only when the event is
triggered (like in this case, addition performed only when at posedge of the clock)
MODULE INSTANTIATION
 Used to instantiate or to connect one module to other modules
A top_level block shall contains multiples submodules
 Ex: a computer shall contains Microprocessor, Memory, I/O Controller, etc.

 Syntax:
module_name label #(parameter) (ports connections);

Module to be Parameters Input/output

instantiated to be passed connections. Input must
(optional) be connected!
INSTANTIATION EXAMPLE
Imagine a system as below
top
a y
sys_a sys_b
m r
s p t z
n q
b
EXERCISE 1
 Create a 4-bit binary counter
 0000  0001  …  1110  1111  0000  …
 Module name: counter
 Inputs: clock, reset
 Outputs: cnt_out[3:0]

 Tips:
 Count value will count up every clock rising edge (posedge)
 Count value will reset to 0 (0000) when reset is high
ANSWER 1
PARAMETERS IN VERILOG
 Parameters:
 Generic values to make the design scalable
 Ex:
 The width of the bus
input [PORT_WIDTH-1:0] in_a;
output [PORT_WIDTH-1:0] out_b;

 To enable or disable a function

assign sum = (EN_FULLADDER) ? (a ^ b ^ c) : (a^b);
PARAMETERS IN VERILOG
 Syntax:
module module_name #(parameter list) (port list);

 Example:
module nbit_adder
#(WIDTH = 16)
(
input [WIDTH-1:0] a,
input [WIDTH-1:0] b,
output [WIDTH:0] c
);
EXAMPLE 2
 Creating a n-bit counter
 IC DESIGN CHALLENGES

 Three points of consideration: Sometimes, we need a very fast chip, but

to have that area must be big and the
cost will be high!
Speed
Sometimes, we want a very power-saving
device… but to do that, our circuit can’t
Area run at very high frequency.

Power In most of the cases, engineers need to

see the need and make some trade-off.
Consumption

Cost
 IC DESIGN CHALLENGES

 Meeting Moore’s Law

 Transistors keep on shrinking
 Number of gates increasing
 IC will become more compact and very high number of gates
 Issues: power, signal integration, delay, faults, etc.