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Multipler ppt-1

This document describes a project to design a power efficient 4-bit multiplier using the Gate Diffusion Input (GDI) technique. The objectives are to reduce power consumption and the number of transistors compared to existing designs like CPL, DPL, and PTL. The proposed design uses GDI cells for the XOR, AND, full adder, and half adder circuits needed for the multiplier. Simulation results will compare the power and performance of the proposed GDI-based multiplier to other designs. Potential applications of this low power multiplier include mobile devices, processors, and digital signal processing.

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Harish Nagulapalli
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95 views

Multipler ppt-1

This document describes a project to design a power efficient 4-bit multiplier using the Gate Diffusion Input (GDI) technique. The objectives are to reduce power consumption and the number of transistors compared to existing designs like CPL, DPL, and PTL. The proposed design uses GDI cells for the XOR, AND, full adder, and half adder circuits needed for the multiplier. Simulation results will compare the power and performance of the proposed GDI-based multiplier to other designs. Potential applications of this low power multiplier include mobile devices, processors, and digital signal processing.

Uploaded by

Harish Nagulapalli
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Miracle Educational Society Group of Institutions

Approved by AICTE, Affiliated to JNTUK, Kakinada.


Miracle City, Bhogapuram Mandal, Vizianagaram Dist.-535216.
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

The project work entitled


Design and Implementation of Power Efficient 4 bit
Multiplier using GDI Technique
Executed by
M.Swetha Madhuri(166C1A0419)
M.Esther Rani(166C1A0420)
K.Sai Kumar(166C1A0415)
P.Nikhil(166C1A0427)

Under the guidance of


Prof. B. Ratna Raju ,
HOD-ECE
OVERVIEW
• ABSTRACT
• INTRODUCTION
• GDI TECHNIQUE
• OBJECTIVE
• EXISTING DESIGN
• PROPOSED DESIGNS
• ADVANTAGES
• APPLICATIONS
ABSTRACT

• Multiplier is a most commonly used circuit in digital devices.


Multiplication is one of the fundamental functions that used in digital
signal processing.
• There are many types of multipliers are available depending upon the
applications.
• We propose a GDI based cell design for 4 bit multiplier. The performance
will be tested using DSCH and Micro Wind tool with 130-nm technology.
• The expected results of the proposed design is more power efficient will
be compared with the existing circuits.
INTRODUCTION

• Now a days, the usage of portable electronic devices has been


increased enormously. These devices require to have less power
consumption and high speed.

• The aim is to design basic arithmetic logic circuits from which we can
obtain low consumption power, less chip area, least propagation delay
and high speed.
GDI TECHNIQUE
• GDI stands for Gate Diffusion Input
• The GDI cell contains three inputs : G ( common
gate input of NMOS and PMOS),P( input to the
source/ drain of PMOS), and N (input to the
source/drain of NMOS).
• The GDI technique allows the uses of less number
of transistors as compared to CMOS logic.
Basic GDI Cell . • The basic GDI cell consist of only two transistors
which are used to implement the basic logic
functions.
Comparison between GDI and CMOS logic:
Comparison between GDI and CMOS gates:
OBJECTIVE
• The main objective is to control power supply and less no. of pmos
and nmos gates. so that we can design our desired circuits which can
easily be used in our modern digital circuits.
The following objectives are:
• To study all basic arithmetic circuits like addition and multiplication.
• To design the 4-bit multiplier with GDI cells.
• To design applications of combinational logic circuits like multiplier
and comparator.
EXISTING DESIGN
• Existing designs are : CPL
DPL
PTL
The above mentioned designs are have some draw backs. They are:
CPL : The CPL suffers from static power consumption due to the low
swing at the gates of the output inverters.
DPL : The large area used due to the presence of pmos transistors.
PTL : The threshold drop across the single channel pass transistors
results in reduced current drive and hence slower operation at reduced
supply voltages.
Direct path static power dissipation could be significant.
Comparisons of existing
designs:
  CTL DPL PTL
Parameter (Complementary Pass- (Double Pass (Pass Transistor
transistor Logic) Logic) Logic)
 

Complexity 10 4 4
Delay(ns) 24.85 26.559 76.121
Power      
Consumed 469.84 10.766 298.79
(nw)
     

Block Diagram
PROPOSED DESIGNS

Proposed multiplier:
The multiplier consist
of nine full adders and
three half adders
Proposed Full Adder:
The Full Adder consist two
XOR gates and two AND gates.

Truth Table:

GDI model Full Adder


Proposed Half Adder

The Half Adder consist


one XOR and one AND
gates

Truth Table:

GDI model Half Adder


GDI XOR gate:

The exclusive OR gate gives high


output when the inputs are not at equal
logic level. The exclusive OR
operation widely used in digital
circuit. It is also called as XOR.
Truth Table:

GDI model XOR gate


GDI AND gate:

The AND gate gives high output


when the all inputs are high.If one
input is low then the output is low

Truth Table:

GDI model AND gate


ADVANTAGES

• low power consumption

• less chip area

• least propagation delay and

• high speed.
APPLICATIONS

• We use a multiplier in several digital signal processing applications.


• we use it to design calculators
mobiles
processors
digital image processors.
THANK YOU

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