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Module 3 NAND and NOR Logic

This document discusses CMOS combinational logic circuits. It explains that CMOS gates consist of two transistor networks: a pull-down network (PDN) of NMOS transistors and a pull-up network (PUN) of PMOS transistors. The rules for implementing AND and OR logic functions using the PDN and PUN are described. Truth tables and explanations of the operation are provided for 2-input CMOS NOR and NAND gates. Implementation of more complex gates like XOR is also briefly covered.

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94 views19 pages

Module 3 NAND and NOR Logic

This document discusses CMOS combinational logic circuits. It explains that CMOS gates consist of two transistor networks: a pull-down network (PDN) of NMOS transistors and a pull-up network (PUN) of PMOS transistors. The rules for implementing AND and OR logic functions using the PDN and PUN are described. Truth tables and explanations of the operation are provided for 2-input CMOS NOR and NAND gates. Implementation of more complex gates like XOR is also briefly covered.

Uploaded by

leevasusan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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VLSI

Ms. Tini Susan Abraham


Assistant Professor, Dept of ECE
SCMS School of Engineering & Technology
CMOS Combinational Circuits
• CMOS logic gate consist of two networks:
1)Pull Down Network(PDN)-NMOS transistors
2) Pull Up Network(PUN) -PMOS transistors

Department of ECE, SCMS School of Engineering & Technology


Department of ECE, SCMS School of Engineering & Technology
Design rule to construct Boolean logic function

RULE I
-Pull Down Network(nmos)
AND operation(.)-nmos devices must be connected in series.
OR operation(+) –nmos devices must be connected in parallel.

Department of ECE, SCMS School of Engineering & Technology


•RULE
  2
-Pull Up Network(pmos)
AND operation(.)-nmos devices must be connected in parallel.
OR operation(+) –nmos devices must be connected in series.
A series connection of PMOS conducts if both inputs are low,
representing a NOR function ( while PMOS transistors in parallel
implement a NAND ()=

Department of ECE, SCMS School of Engineering & Technology


CMOS 2 input NOR gate
•  Y=
OR operation-nmos(PDN) in parallel
pmos(PUN) in series
TRUTH TABLE
A B Y
0 0 1
0 1 0
1 0 0
1 1 0

Department of ECE, SCMS School of Engineering & Technology


Working
• CASE-1 : A – 0 & B – 0
• As A and B both are low, both the pMOS will be ON and both the nMOS
will be OFF.
• The output Vout will get two paths through two ON pMOS to get connected
with Vdd.
• The output will be charged to the Vdd level.
• The output line will not get any path to the GND as both the nMOS are off.
• So, there is no path through which the output line can discharge. The
output line will maintain the voltage level at Vdd; so Vout= High.

Department of ECE, SCMS School of Engineering & Technology


• CASE-2 : A – 0 & B – 1
• As A=0 and B=1, the pmos transistors Q1will be ON and Q2 will
be OFF.
• For nmos transistors Q3 will be OFF and Q4 will be ON.
• Both nmos are in parallel(Q3 and Q4). Though Q3 is OFF, still the
output line will get a path through Q4 to get connected with Vss.
• Both pmos are in series. As Q2 is OFF, so Vout will not be able to find a
path to VDD . This in turn results the Vout to be maintained at the level
of ground; so,  Vout =Low.

Department of ECE, SCMS School of Engineering & Technology


• CASE-3 : A – 1 & B – 0
• As A=1 and B=0, the pmos transistors Q1will be OFF and Q2 will
be ON.
• For nmos transistors Q3 will be ON and Q4 will be OFF.
• Both nmos are in parallel(Q3 and Q4). Though Q4 is OFF, still the
output line will get a path through Q3 to get connected with Vss.
• Both pmos are in series. As Q1 is OFF, so Vout will not be able to find a
path to VDD . This in turn results the Vout to be maintained at the level
of ground; so,  Vout =Low.

Department of ECE, SCMS School of Engineering & Technology


• CASE-4 : A – 1 & B – 1
• As A and B both are high, both the pMOS will be OFF and both the
nMOS will be ON.
• The output Vout will get two paths through two ON nMOS to get
connected with Vss.
• The output will be discharged to the Vss  level.
• The output line will not get any path toVDD as both the pMOS are off.
• So, there is no path through which the output line can charge. The
output line will maintain the voltage level at Vss; so Vout= LOW.
Department of ECE, SCMS School of Engineering & Technology
CMOS 2 input NAND gate
•  Y=
AND operation-nmos(PDN) in series
AND operation pmos(PUN) in parallel
TRUTH TABLE
A B Y

0 0 1

0 1 1

1 0 1

1 1 0

Department of ECE, SCMS School of Engineering & Technology


Working
• CASE-1 : A – 0 & B – 0
• As A and B both are low, both the pMOS will be ON and both the nMOS
will be OFF.
• The output Vout will get two paths through two ON pMOS to get connected
with Vdd.
• The output will be charged to the Vdd level.
• The output line will not get any path to the GND as both the nMOS are off.
• So, there is no path through which the output line can discharge. The
output line will maintain the voltage level at Vdd; so Vout= High.

Department of ECE, SCMS School of Engineering & Technology


• CASE-2 : A – 0 & B – 1
• As A=0 and B=1, the pmos transistors Q1will be ON and Q2 will
be OFF.
• For nmos transistors Q3 will be OFF and Q4 will be ON.
• Both pmos are in parallel(Q1 and Q2). Though Q2 is OFF, still the
output line will get a path through Q1 to get connected with VDD.
• Both nmos are in series. As Q3 is OFF, so Vout will not be able to find a
path to VSS . This in turn results the Vout to be maintained at the level
of VDD ; so,  Vout =High.

Department of ECE, SCMS School of Engineering & Technology


• CASE-3 : A – 1 & B – 0
• As A=1 and B=0, the pmos transistors Q1will be OFF and Q2 will
be ON.
• For nmos transistors Q3 will be ON and Q4 will be OFF.
• Both pmos are in parallel(Q1 and Q2). Though Q1 is OFF, still the
output line will get a path through Q2 to get connected with VDD.
• Both nmos are in series. As Q4 is OFF, so Vout will not be able to find a
path to Vss . This in turn results the Vout to be maintained at the level
of VDD; so,  Vout =HIGH.

Department of ECE, SCMS School of Engineering & Technology


• CASE-4 : A – 1 & B – 1
• As A and B both are high, both the pMOS will be OFF and both the
nMOS will be ON.
• The output Vout will get two paths through two ON nMOS to get
connected with Vss.
• The output will be discharged to the Vss  level.
• The output line will not get any path toVDD as both the pMOS are off.
• So, there is no path through which the output line can charge. The
output line will maintain the voltage level at Vss; so Vout= LOW.
Department of ECE, SCMS School of Engineering & Technology
Complex Logic Gates
•Implementation
 
• Z=

Department of ECE, SCMS School of Engineering & Technology


 
Z=

Department of ECE, SCMS School of Engineering & Technology


Two input XOR gate

•  Method 1
Z==
Method 2

B+A =XOR

Department of ECE, SCMS School of Engineering & Technology


•

Department of ECE, SCMS School of Engineering & Technology

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