B.Tech – CSE – Sem.

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15CS202 – DIGITAL SYSTEM DESIGN
(Regulations 2015)

UNIT -IV
SYNCHRONOUS SEQUENTIAL
CIRCUITS
OUTLINE
• FlipFlops SR,D,JK,T
• Analysis of Synchronous Sequential Circuit
• State Reduction and Assignment
• Design-Sequence Detector
• BCD Counter
• Registers-Shift Register
• Analysis
 Sequential Circuits

Every digital system is likely to have combinational circuits,

most systems encountered in practice also include storage
elements, which require that the system be described in term
of sequential logic.

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Synchronous Clocked Sequential Circuit
A sequential circuit may use many flip-flops to store as many
bits as necessary. The outputs can come either from the
combinational circuit or from the flip-flops or both.

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 Latches --SR Latch
The SR latch is a circuit with two cross-coupled NOR gates or
two cross-coupled NAND gates. It has two inputs labeled S
for set and R for reset.

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SR Latch with NAND Gates

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 SR Latch with Control Input
The operation of the basic SR latch can be modified by
providing an additional control input that determines when
the state of the latch can be changed. In Fig. 5-5, it consists
of the basic SR latch and two additional NAND gates.

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 D Latch

One way to eliminate the undesirable condition of the

indeterminate state in SR latch is to ensure that inputs S
and R are never equal to 1 at the same time in Fig 5-5. This
is done in the D latch.

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Graphic Symbols for latches
A latch is designated by a rectangular block with inputs on
the left and outputs on the right. One output designates the
normal output, and the other designates the complement
output.

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 Flip-Flops

The state of a latch or flip-flop is switched by a change in

the control input. This momentary change is called a trigger
and the transition it cause is said to trigger the flip-flop. The
D latch with pulses in its control input is essentially a flip-flop
that is triggered every time the pulse goes to the logic 1
level. As long as the pulse input remains in the level, any
changes in the data input will change the output and the
state of the latch.

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Clock Response in Latch

In Fig (a) a positive level response in the control input

allows changes, in the output when the D input changes
while the clock pulse stays at logic 1.

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Clock Response in Flip-Flop

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Edge-Triggered D Flip-Flop

The first latch is called the master and the second the
slave. The circuit samples the D input and changes its output
Q only at the negative-edge of the controlling clock.

D 110011…
Y 110011…
Q ? 1 1 0 0 1 ….
CLK
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D-Type Positive-Edge-Triggered Flip-
Flop
Another more efficient construction of an edge-triggered D
flip-flop uses three SR latches. Two latches respond to the
external D(data) and CLK(clock) inputs. The third latch
provides the outputs for the flip-flop.

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Graphic Symbol for Edge-
Triggered D Flip-Flop

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Other Flip-Flops -JK Flip-Flop

There are three operations that can be performed with a

flip-flop: set it to 1, reset it to 0, or complement its output.
The JK flip-flop performs all three operations. The circuit
diagram of a JK flip-flop constructed with a D flip-flop and
gates.

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JK Flip-Flop
The J input sets the flip-flop to 1, the K input resets it to 0,
and when both inputs are enabled, the output is
complemented. This can be verified by investigating the
circuit applied to the D input:
D = J Q` + K` Q

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 T Flip-Flop
The T(toggle) flip-flop is a complementing flip-flop and
can be obtained from a JK flip-flop when inputs J and K
are tied together.

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T Flip-Flop
The T flip-flop can be constructed with a D flip-flop and
an exclusive-OR gates as shown in Fig. (b). The
expression for the D input is
D=T Q = TQ` + T`Q

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Characteristic Equations

D flip-flop Characteristic Equations

Q(t + 1) = D

JK flip-flop Characteristic Equations

Q(t + 1) = JQ` + K`Q

T flip-flop Characteristic Equations

Q(t + 1) = T Q = TQ` + T`Q

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Direct Inputs
Some flip-flops have asynchronous inputs that are used to
force the flip-flop to a particular state independent of the clock.
The input that sets the flip-flop to 1 is called present or direct
set. The input that clears the flip-flop to 0 is called clear or
direct reset. When power is turned on a digital system, the state
of the flip-flops is unknown. The direct inputs are useful for
bringing all flip-flops in the system to a known starting state
prior to the clocked operation.

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D Flip-Flop with Asynchronous Reset

A positive-edge-triggered D flip-flop with asynchronous reset

is shown in Fig(a).

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D Flip-Flop with Asynchronous Reset

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Analysis of Clocked Sequential Circuits

The analysis of a sequential circuit consists of obtaining a

table or a diagram for the time sequence of inputs, outputs,
and internal states. It is also possible to write Boolean
expressions that describe the behavior of the sequential
circuit. These expressions must include the necessary time
sequence, either directly or indirectly.

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Example of Sequential Circuit

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State Equation

A(t+1) = A(t) x(t) + B(t) x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that specifies

the condition for a flip-flop state transition. The left side of
the equation with (t+1) denotes the next state of the flip-
flop one clock edge later. The right side of the equation is
Boolean expression that specifies the present state and
input conditions that make the next state equal to 1.

Y(t) = (A(t) + B(t)) x(t)`

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State Equations

The behavior of a clocked sequential circuit can be

described algebraically by means of state equations. A state
equation specifies the next state as a function of the present
state and inputs. Consider the sequential circuit shown in
Fig. 5-15. It consists of two D flip-flops A and B, an input x
and an output y.

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State Table
The time sequence of inputs, outputs, and flip-flop states
can be enumerated in a state table (sometimes called
transition table).

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State Diagram

The information available in a state table can be

represented graphically in the form of a state diagram. In
this type of diagram, a state is represented by a circle, and
the transitions between states are indicated by directed
lines connecting the circles.

1/0 : means input =1

output=0

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Flip-Flop Input Equations
The part of the combinational circuit that generates
external outputs is descirbed algebraically by a set of
Boolean functions called output equations. The part of the
circuit that generates the inputs to flip-flops is described
algebraically by a set of Boolean functions called flip-flop
input equations. The sequential circuit of Fig. 5-15 consists
of two D flip-flops A and B, an input x, and an output y. The
logic diagram of the circuit can be expressed algebraically
with two flip-flop input equations and an output equation:

DA = Ax + Bx
DB = A`x
y = (A + B)x`
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Analysis with D Flip-Flop

The circuit we want to analyze is described by the input

equation DA = A x y
The DA symbol implies a D flip-flop with output A. The x
and y variables are the inputs to the circuit. No output
equations are given, so the output is implied to come from
the output of the flip-flop.

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 Analysis with D Flip-Flop
The binary numbers under Axy are listed from 000 through
111 as shown in Fig. 5-17(b). The next state values are
obtained from the state equation A(t+1) = A x y
The state diagram consists of two circles-one for each state
as shown in Fig. 5-17(c)

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Analysis with JK Flip-Flops

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Analysis with JK Flip-Flop

The circuit can be specified by the flip-flop input equations

JA = B KA = Bx`
JB = x` KB = A`x + Ax` = A x

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Analysis with JK Flip-Flops
A(t + 1) = JA` + K`A
B(t + 1) = JB` + K`B
Substituting the values of JA and KA from the input
equations, we obtain the state equation for A:

A(t + 1) = BA` + (Bx`)`A = A`B + AB` +Ax

The state equation provides the bit values for the column
under next state of A in the state table. Similarly, the state
equation for flip-flop B can be derived from the characteristic
equation by substituting the values of JB and KB:

B(t + 1) = x`B` + (A x)`B = B`x` + ABx + A`Bx`

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Analysis with JK Flip-Flops

The state diagram of the sequential circuit is shown in Fig

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Analysis With T Flip-Flops
Characteristic equation
Q(t + 1) = T Q = T`Q + TQ`

00/0 : means
state is 00
output is 0

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Analysis With T Flip-Flops

Consider the sequential circuit shown in Fig. 5-20. It has

two flip-flops A and B, one input x, and one output y. It
can be described algebraically by two input equations and
an output equation:
Use present state
as inputs
TA = Bx
TB = x
y = AB

A(t+1)=(Bx)’A+(Bx)A’
=AB’+Ax’+A’Bx

B(t+1)=xB

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Synthesis Using T Flip-Flops

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State Reduction and Assignment
State Reduction and Assignment
(Contd.)
State Reduction and Assignment
(Contd.)
State Reduction and Assignment
(Contd.)
State Reduction and Assignment
(Contd.)

State Assignment

State Binary Gray CodeOne-Hot

a 000 000 00001
b 001 001 00010
c 010 011 00100
d 011 010 01000
e 100 110 10000
State Reduction and Assignment
(Contd.)
Reduced State Table:
Binary State Assignment
Next State Output
State x=0 x=1 x=0 x=1

001 000 001 0 0

010 010 011 0 0

011 000 011 0 0

100 100 011 0 1

101 000 011 0 1

State Reduction and Assignment
(Contd.)
Reduced State Table:
Binary State Assignment
Next State Output
State
x=0 x=1 x=0 x=1
001
000 001 0 0
010
010 011 0 0
011
000 011 0 0
100
100 011 0 1
101
000 011 0 1
Design Procedure

• Develop State Diagram From Specs

• Reduce States
• Assign Binary values to States
• Write Binary-coded State Table
• Choose Flip-Flops
• Derive Input and Output Equations
• Draw the Logic Diagram
Develop State Diagram:
Sequence Detector
• Detect 3 or more 1s in sequence (a Moore Model)
D Flip-Flop Input Equations

State Input Next State Output

A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 0
0 1 1 1 0 0
1 0 0 0 0 0
1 0 1 1 1 0
1 1 0 0 0 1
1 1 1 1 1 1
A(t+1) = DA(A,B,x) = (3,5,7)
B(t+1) = DB(A,B,x) = (1,5,7)
Input equations come
directly from the nexty(A,B,x) = (6,7)
state in D Flip-Flop
design
Simplified Boolean Equations
Sequence Detector: D Flip-Flops
Using JK or T Flip-Flops

1. Develop Excitation Table Using Excitation Tables

JK Flip-Flop T Flip-Flop

Q(t) Q(t+1) J K Q(t) Q(t+1) T

0 0 0 X 0 0 0
0 1 1 X 0 1 1
1 0 X 1 1 0 1
1 1 X 0 1 1 0
State Table: JK Flip-Flop Inputs

Present Next
State Input State Flip-Flop Inputs
A B x A B JA KA JB KB
0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0
0 1 0 0 1 0 1 0 1
1 0 1 1 0 1 0 1 0
1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0
Maps for J and K Input Equations
JK Flip-Flop Sequence Detector
Registers and Counter

• The filp-flops are essential component in clocked

sequential circuits.
• Circuits that include filp-flops are usually
classified by the function they perform. Two such
circuits are registers and counters.
• An n-bit register consists of a group of n flip-flops
capable of storing n bits of binary information.

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UP-DOWN COUNTER
BCD Counter

• Because of the return to 0 after a count of 9, a

BCD counter does not have a regular pattern
as in a straight binary count.
• To derive the circuit of a BCD synchronous
counter, it is necessary to go through a
sequential circuit design procedure.

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BCD Counter

State Table for BCD Counter

Present State Next State Output Flip-Flop inputs

Q8 Q4 Q2 Q1 Q8 Q4 Q2 Q1 Y TQ8 TQ4 TQ2 TQ1
0 0 0 0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 1 0 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 0 1
0 0 1 1 0 1 0 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 0 1
0 1 0 1 0 1 1 0 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 0 1
0 1 1 1 1 0 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 0 1
1 0 0 1 0 0 0 0 1 0 0 0 1
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BCD COUNTER
BCD Counter

• The flip flop input equations can be simplified

by means of maps. The simplified functions are
– TQ1=1
– TQ2=Q8’Q1
– TQ4=Q2Q1
– TQ8=Q8Q1+Q4Q2Q1
– y=Q8Q1
• The circuit can be easily drawn with four T flip-
flops, five AND gates, and one OR gate.

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An Example of Counter
Registers

• In its broadest definition, a register consists a

group of flip-flops and gates that effect their
transition.
– The flip-flops hold the binary information.
– The gates determine how the information is
transferred into the register.
• Counters are a special type of register.
• A counter goes through a predetermined
sequence of states.
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Registers

• Fig 6-1 shows a register

constructed with four D-
type filpflops.
• “Clock” triggers all flip-
folps on the positive edge
of each pulse.
• “Clear” is useful for
clearing the register to all
0’s prior to its clocked
operation.

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Shift Registers

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Shift Registers

• A register capable of shifting its binary

information in one or both direction is called a
shift register.
• All flip-flops receive common clock pulses,
which activate the shift from one stage to the
next.
• The simplest possible shift register is one that
uses only flip-flops, as shown in Fig. 6-3.

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